The PWM count register (PWMCNT) can be read at any time without affecting its val-
ue. A read must be a word access to ensure coherence, but byte accesses can be
made if coherence is not needed. The counter is cleared to $0000 during reset and is
a read-only register except in freeze or test mode.
Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers
provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the
SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the
SFB bit in the same register.
PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast
mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7]
are used. The period of a PWM output in is 128 times longer than the fast mode period.
Table 7-3 shows a range of PWM output frequencies using a 16.78-MHz system clock
and 20.97-MHz system clock.
Table 7-3 PWM Frequency Ranges
Using 16.78-MHz/20.97-MHz System Clocks
PPR
[2:0]
Prescaler Tap
16.78 MHz 20.97 MHz
SFA/B = 0
SFA/B = 1
7
16.78 MHz
20.97 MHz
41 kHz
16.78 MHz 20.97 MHz
000 Div 2 = 8.39 MHz Div 2 = 10.5 MHz
001 Div 4 = 4.19 MHz Div 4 = 5.25 MHz
010 Div 8 = 2.10 MHz Div 8 = 2.62 MHz
011 Div 16 = 1.05 MHz Div 16 = 1.31 MHz
100 Div 32 = 524 kHz Div 32 = 655 kHz
101 Div 64 = 262 kHz Div 64 = 328 kHz
110 Div 128 = 131 kHz Div 128 = 164 kHz
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
5.0 Hz
20.5 kHz
10.2 kHz
5.15 kHz
2.56 kHz
1.28 kHz
641 Hz
4.0 Hz
111
PCLK
PCLK
PCLK/256
PCLK/256
PCLK/32768 PCLK/32768
7.11.2 PWM Function
The pulse width values of the PWM outputs are determined by control registers PWMA
and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16-
bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit
register. A value of $00 loaded into either register causes the corresponding output pin
to output a continuous logic level zero signal. A value of $80 causes the corresponding
output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which
corresponds to an output which is at logic level one for 255/256 of the cycle.
Setting the F1A (for PWMA) or F1B (for PWMB) bits in the register causes the corre-
sponding pin to output a continuous logic level one signal. The logic level of the asso-
ciated pin does not change until the end of the current cycle. F1A and F1B are the
lower two bits of CFORC, but can be accessed at the same word address as PWMC.
Data written to PWMA and PWMB is not used until the end of a complete cycle. This
prevents spurious short or long pulses when register values are changed. The current
duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PW-
MBUFB). The new value is transferred from the PWM register to the buffer register at
the end of the current cycle.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-17
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
