synchronized with the system clock so that latching of TCNT content and counter in-
crementation occur on opposite half-cycles of the system clock. Inputs have hystere-
sis. Capture of any transition longer than two system clocks is guaranteed; any
transition shorter than one system clock has no effect.
Figure 7-4 shows the relationship of system clock to synchronizer output. The value
latched into the capture register is the value of the counter several system clock cycles
after the transition that triggers the edge detection logic. There can be up to one clock
cycle of uncertainty in latching of the input transition. Maximum time is determined by
the system clock frequency.
The input capture register is a 16-bit register. A word access is required to ensure co-
herency. If coherency is not required, byte accesses can be used to read the register.
Input capture registers can be read at any time without affecting their values.
F (PH1)
SYS
CAPTURE/COMPARE
CLOCK
7
$0101
$0102
TCNT
EXTERNAL PIN
SYNCHRONIZER
OUTPUT
$0102
CAPTURE REGISTER
ICF FLAG
1153A
Figure 7-4 Input Capture Timing Example
An input capture occurs every time a selected edge is detected, even when the input
capture status flag is set. This means that the value read from the input capture regis-
ter corresponds to the most recent edge detected, which may not be the edge that
caused the status flag to be set.
7.8.3 Output Compare Functions
Each GPT output compare pin has an associated 16-bit compare register and a 16-bit
comparator. Each output compare function has an associated status flag, and can
cause the GPT to make an interrupt service request. Output compare logic is designed
to prevent false compares during data transition times.
MOTOROLA
7-12
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
