欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC68331CFC16 参数 Datasheet PDF下载

MC68331CFC16图片预览
型号: MC68331CFC16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
 浏览型号MC68331CFC16的Datasheet PDF文件第168页浏览型号MC68331CFC16的Datasheet PDF文件第169页浏览型号MC68331CFC16的Datasheet PDF文件第170页浏览型号MC68331CFC16的Datasheet PDF文件第171页浏览型号MC68331CFC16的Datasheet PDF文件第173页浏览型号MC68331CFC16的Datasheet PDF文件第174页浏览型号MC68331CFC16的Datasheet PDF文件第175页浏览型号MC68331CFC16的Datasheet PDF文件第176页  
7.10 Pulse Accumulator  
The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can  
operate in external event counting or gated time accumulation modes. Figure 7-5 is a  
block diagram of the pulse accumulator.  
In event counting mode, the counter increments each time a selected transition of the  
pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the sys-  
tem clock divided by four.  
In gated time accumulation mode a clock increments PACNT while the PAI pin is in  
the active state. There are four possible clock sources.  
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator  
flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse  
accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has  
rolled over from $FF to $00. This can be used to extend the range of the counter be-  
yond eight bits.  
An interrupt request can be made when each of the status flags is set. However, op-  
eration of the PAI interrupt depends on operating mode. In event counting mode, an  
interrupt is requested when the edge being counted is detected. In gated mode, the  
request is made when the PAI input changes from active to inactive state. Interrupt re-  
quests are enabled by the PAOVI and PAII bits in the TMSK2 register.  
7
Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.  
The PAMOD bit selects event counting or gated operation. In event counting mode,  
the PEDGE control bit determines whether a rising or falling edge is detected; in gated  
mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the  
clock source used in gated mode.  
PACTL and PACNT are implemented as one 16-bit register, but can be accessed with  
byte or word access cycles. Both registers are cleared at reset, but the PAIS and  
PCLKS bits show the state of the PAI and PCLK pins.  
The PAI pin can also be used for general-purpose input. The logic state of the PAIS  
bit in PACTL shows the state of the pin.  
MOTOROLA  
7-14  
GENERAL-PURPOSE TIMER  
MC68331  
USER’S MANUAL  
 复制成功!