Pulse-width modulation A and B (PWMA/PWMB) output pins can serve as general-
purpose outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in
the compare force (CFORC) and PWM control (PWMC) registers, respectively, control
their operation.
7.7 Prescaler
Capture/compare and PWM units have independent 16-bit free-running counters as a
main timing component. These counters derive their clocks from the prescaler or from
the PCLK input. Figure 7-2 is a prescaler block diagram.
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler
outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-
vided. Connected to these outputs are two multiplexers, one for the capture/compare
unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]
in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC).
7
After reset, the GPT is configured to use system clock divided by four for TCNT and
system clock divided by two for PWMCNT. Initialization software can change the divi-
sion factor. The PPR bits can be written at any time but the CPR bits can only be writ-
ten once after reset unless the GPT is in test or freeze mode.
The prescaler can be read at any time. In freeze mode the prescaler can also be writ-
ten. Word accesses must be used to ensure coherency. If coherency is not needed
byte accesses can be used. The prescaler value is contained in bits [8:0] while bits
[15:9] are unimplemented and are read as zeros.
MOTOROLA
7-8
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
