Freescale SMeCm33i3c89onductor, Inc.
Parameter
SCLK Clock High Time
SCLK Clock Low Time
Symbol
twSCLKH
twSCLKL
Min
175
175
Typ
Max
Unit
Test Conditions
ns
ns
Falling Edge of CSB to Rising
Edge of SCLK
tlead
250
250
50
50
ns
ns
Falling Edge of SCLK to Rising
Edge of CSB
tlead
SI to Falling Edge of SCLK
Falling Edge of SCLK to SI
SO Rise Time (CL = 220pF)
SO Fall Time (CL = 220pF)
tSISU
tSI(hold)
trSO
125
125
25
25
25
25
ns
ns
ns
ns
75
75
tfSO
SI, CSB, SCLK Incoming
Signal Rise Time
trSI
200
200
ns
SI, CSB, SCLK Incoming
Signal Fall Time
tfSI
Time from Falling Edge of CSB to SO
Low Impedance
tSO(en)
tSO(dis)
200
200
ns
High Impedance
Time from Rising Edge of
SCLK to SO Data Valid
0.2 V1 or V2≤SO≥ 0.8V1 or
tvalid
50
125
V2, CL=200pF
SOFTWARE WATCHDOG TIMINGS
(note 1: software watchdog timing accuracy are based on the running mode oscillator tolerance)
normal request, normal and
standby modes. (Note 1)
Running mode oscillator tolerance
-12
+12
%
Software Watchdog Timing 1
Software Watchdog Timing 2
Software Watchdog Timing 3
Software Watchdog Timing 4
Software Watchdog Timing 5
Software Watchdog Timing 6
Software Watchdog Timing 7
Software Watchdog Timing 8
SWt1
SWt2
SWt3
SWt4
SWt5
SWt6
SWt7
SWt8
4.4
8.8
17.6
28
5
5.6
11.2
22.4
36
ms
ms
ms
ms
ms
ms
ms
ms
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
10
20
32
44.8
65
51
58
74
83
88
100
202
112
226
178
FORCED WAKE-UP AND CYCLIC SENSE TIMINGS
(note 2: cyclic sense and forced wake up timing accuracy are based on the sleep mode oscillator tolerance)
Sleep mode oscillator tolerance
Cyclic Sense / FWU timing 1
Cyclic Sense / FWU timing 2
Cyclic Sense / FWU timing 3
-30
+30
41.6
83.2
166.4
%
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
sleep mode (Note 2)
CYt1
CYt2
CYt3
22.4
44.8
89.6
32
64
ms
ms
ms
128
For More Information On This Product,
MC33389
MOTOROLA
8
Go to: www.freescale.com
MOTOROLA [ MOTOROLA ]
