V58C2128(804/404/164)S
AC Operating Conditions & Timming Specification
AC Operating Conditions
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Max
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VREF + 0.31
1
2
3
4
VREF - 0.31
VDDQ+0.6
V
0.62
V
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Note:
1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIMING for PC333/PC266/PC200 -Absolute
Specifications
(Notes: 1-5, 14-17) (0°C < T < 70°C; V Q = +2.5V ±0.2V, +2.5V ±0.2V)
A
DD
AC CHARACTERISTICS
-6
-7
-75
-8
SYM-
BOL
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Access window of DQs from CK/CK
CK high-level width
tAC
tCH
-0.7
0.45
0.45
6
0.7
0.55
0.55
12
-0.75 0.75 -0.75 0.75
-0.8
0.8
ns
tCK
tCK
ns
0.45
0.45
7
0.55
0.55
12
0.45
0.45
7.5
0.55 0.45 0.55
0.55 0.45 0.55
30
30
52
52
CK low-level width
tCL
Clock cycle time
CL = 2.5
CL = 2
tCK (2.5)
tCK (2)
12
12
8
12
12
7.5
12
7.5
12
10
10
ns
DQ and DM input hold time relative to
DQS
tDH
tDS
0.45
0.45
1.5
0.5
0.5
0.5
0.5
0.6
0.6
2
ns
ns
ns
26,31
26,31
31
DQ and DM input setup time relative to
DQS
DQ and DM input pulse width (for each in-
put)
tDIPW
1.75
1.75
Access window of DQS from CK/CK
DQS input high pulse width
DQS input low pulse width
tDQSCK -0.6
0.6
-0.75 0.75 -0.75 0.75
-0.8
0.35
0.35
0.8
0.6
ns
tDQSH
tDQSL
0.35
0.35
0.35
0.35
0.35
0.35
tCK
tCK
DQS-DQ skew, DQS to last DQ valid,
per group, per access
tDQSQ
tDQSS
0.45
1.25
0.5
0.5
ns
25,26
Write command to first DQS latching tran-
sition
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25 0.75 1.25
tCK
tCK
tCK
DQS falling edge to CK rising - setup time tDSS
0.2
0.2
DQS falling edge from CK rising - hold
tDSH
0.2
0.2
0.2
time
Half clock period
tHP
tCH,
tCL
tCH,
tCL
tCH,
tCL
tCH,
tCL
ns
34
V58C2128(804/404/164)S Rev. 1.6 March 2002
35
MOSEL [ MOSEL VITELIC, CORP ]
