V58C2128(804/404/164)S
IDD Specifications and Conditions
(0°C < TA < 70°C, VDDQ=25V+ 0.2V, VDD=2.5 Ia2V)
Version
Conditions
Symbol -6
-7 -7.5 -8
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200,
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock cycle
IDD0
115 100
95
85
Operating current - One bank operation; One bank open, BL=4
IDD1
165 150 150 135
Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max);
IDD2P
27
50
25
45
25
45
23
40
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs IDD2F
changing once per clock cycle; Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK =
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable IDD2Q
with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
38
35
35
30
35
30
32
25
Active power - down standby current; one bank active; power-down mode; CKE=< VIL (max);
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166MHZ for DDR333B; Vin =
Vref for DQ,DQS and DM
IDD3P
IDD3N
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - pre-
charge; tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166Mhz
for DDR333B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
50
45
45
35
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active;
address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200,
CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B, CL=2.5 at
tCK=166Mhz for DDR333B; 50% of data changing at every burst; lout = 0 m A
IDD4R 180 160 160 140
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active ad-
dress and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2
at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs
changing twice per clock cycle, 50% of input data changing at every burst
IDD4W 180 150 150 120
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A
& DDR266B at 133Mhz, 12*tCK for DDR333B; distributed refresh
IDD5
210 200 200 190
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200,
IDD6
IDD7
2
2
2
2
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B.
Operating current - Four bank operation; Four bank interleaving with BL=4
285 280 280 275
V58C2128(804/404/164)S Rev. 1.6 March 2002
34
MOSEL [ MOSEL VITELIC, CORP ]
