V54C3256(16/80/40)4V(T/S/B)
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Burst Write Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Power Down Mode
13. Self Refresh (Entry and Exit)
14. Auto Refresh (CBR)
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
20
MOSEL [ MOSEL VITELIC, CORP ]
