V54C3256(16/80/40)4V(T/S/B)
AC Characteristics 1,2, 3
T = 0 to 70 °C; V = 0 V; V = 3.3 V ± 0.3 V, t = 1 ns
A
SS
DD
T
Limit Values
-7PC -7
-8PC
-6
#
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
Clock Cycle Time
s
CAS Latency = 3
CAS Latency = 2
6
–
–
7
–
–
7
–
–
8
–
–
ns
ns
7.5
7.5
10
10
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
166
133
–
–
143
133
–
–
143
100
–
–
125
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
2, 4
–
_
5.4
5.4
–
_
5.4
5.4
–
_
5.4
6
–
_
6
6
ns
ns
CAS Latency = 2
4
5
6
tCH
tCL
tT
Clock High Pulse Width
Clock Low Pulse Width
Transition Tim
2.5
2.5
0.3
–
–
2.5
2.5
0.3
–
–
2.5
2.5
0.3
–
–
3
3
–
–
ns
ns
ns
1.2
1.2
1.2
0.5
10
Setup and Hold Times
7
8
tIS
tIH
Input Setup Time
1.5
0.8
1.5
0.8
12
–
–
–
–
–
6
1.5
0.8
1.5
0.8
14
0
–
–
–
–
–
7
1.5
0.8
1.5
0.8
14
0
–
–
–
–
–
7
2
1
–
–
–
–
–
8
ns
ns
ns
ns
ns
ns
5
5
5
5
Input Hold Time
9
tCKS
tCKH
tRSC
tSB
Input Setup Time
2
10
11
12
CKE Hold Time
1
Mode Register Set-up Time
Power Down Mode Entry Time
16
0
0
Common Parameters
13
14
15
16
17
18
tRCD
tRP
tRAS
Row to Column Delay Time
Row Precharge Time
Row Active Time
12
15
–
–
15
15
–
–
15
15
–
–
20
20
–
–
ns
ns
6
6
6
6
6
40 100K 42 100K 42 100K 45
100k
–
ns
tRC
tRRD
tCCD
Row Cycle Time
60
–
–
–
60
14
1
–
–
–
60
14
1
–
–
–
60
16
1
ns
Activate(a) to Activate(b) Command Period 12
–
ns
CAS(a) to CAS(b) Command Period
1
–
CLK
Refresh Cycle
19
20
tREF
Refresh Period (8192 cycles)
Self Refresh Exit Time
—
64
—
64
—
64
—
64
ms
tSREX
1
—
1
—
1
—
1
—
CLK
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
18
MOSEL [ MOSEL VITELIC, CORP ]
