MOSEL VITELIC
Address Input for Mode Set (Mode Register Operation)
V54C365164VC
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Mode Register
Operation Mode
CAS Latency
BT
Burst Length
Operation Mode
BA1 BA0 A11 A10 A9 A8 A7
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Mode
Burst Read/Burst
Write
Burst Read/Single
Write
Burst Type
A3
0
1
Type
Sequential
Interleave
CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
4
Reserve
Reserve
Reserve
Burst Length
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Length
Sequential
1
2
4
8
Reserve
Reserve
Reserve
Full Page
Interleave
1
2
4
8
Reserve
Reserve
Reserve
Reserve
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle latch-
es the sense amplifiers. The maximum t
RAS
or the
refresh interval time limits the number of random col-
umn accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed burst
length, alternate access and precharge operations
on two or more banks can realize fast serial data
access modes among many different pages. Once
two or more banks are activated, column to column
interleave operation can be done between different
pages.
V54C365164VC Rev. 0.8 July 2001
7
MOSEL [ MOSEL VITELIC, CORP ]
