MOSEL VITELIC
Operation Definition
V54C365164VC
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Device
State
Idle
3
Active
3
Active
3
Active
3
Active
3
Any
Any
Idle
Any
Any
Idle
Idle
Idle
(Self Refr.)
Idle
Active
5
Any
(Power
Down)
Active
Active
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
CKE
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
L
L
L
L
L
L
L
L
H
L
L
H
RAS
L
H
H
H
H
L
L
L
H
X
L
L
X
H
X
H
X
H
X
X
CAS
H
L
L
L
L
H
H
L
H
X
L
L
X
H
X
H
X
H
X
X
WE
H
H
H
L
L
L
L
L
H
X
H
H
X
X
X
X
X
L
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
A0-9,
A11
V
V
V
V
V
X
X
V
X
X
X
X
A10
V
L
H
L
H
L
H
V
X
X
X
X
BS0
BS1
V
V
V
V
V
V
X
V
X
X
X
X
L
H
L
H
X
X
X
X
Power Down Entry
H
L
L
H
X
X
X
X
Power Down Exit
L
H
L
X
X
X
X
X
X
Data Write/Output Enable
Data Write/Output Disable
H
H
X
X
L
H
X
X
X
X
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.
V54C365164VC Rev. 0.8 July 2001
5