MO SEL VITELIC
V29LC51001
Functional Block Diagram
1,048,576 Bit
Memory Cell Array
X-Decoder
A0–A16
Address buffer & latches
Y-Decoder
CE
OE
WE
Control Logic
I/O Buffer & Data Latches
I/O0–I/O7
51001-05
Capacitance (1,2)
Symbol
Parameter
Test mSetup
Typ.
Max.
Units
pF
C
C
C
Input Capacitance
V
= 0
6
8
8
8
IN
IN
Output Capacitance
Control Pin Capacitance
V
= 0
12
10
pF
OUT
IN2
OUT
V
= 0
pF
IN
NOTE:
1. Capacitance is sampled and not 100% tested.
2.
T
= 25°C, V = 5V ± 10%, f = 1 MHz.
A
CC
(1)
Latch Up Characteristics
Parameter
Min.
-1
Max.
Unit
V
Input Voltage with Respect to GND on A , OE
+13
9
Input Voltage with Respect to GND on I/O, address or control pins
Current
-1
V
+ 1
V
CC
V
-100
+100
mA
CC
NOTE:
1. Includes all pins except V . Test conditions: V = 5V, one pin at a time.
CC
CC
AC Test Load
+5.0 V
IN3064
or Equivalent
2.7 kΩ
Device Under
Test
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
51001-06
CL = 100 pF
6.2 kΩ
V29LC51001 Rev. 0.5 October 2000
3
MOSEL [ MOSEL VITELIC, CORP ]
