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V29LC51001 参数 Datasheet PDF下载

V29LC51001图片预览
型号: V29LC51001
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位131,072 ×8位的5伏CMOS FLASH MEMORY [1 MEGABIT 131,072 x 8 BIT 5 VOLT CMOS FLASH MEMORY]
分类和应用:
文件页数/大小: 12 页 / 55 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC
FUNCTIONAL DESCRIPTION
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
V29LC51001
512
512
512
V29LC51001
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
512
00000H
L51001-13
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE signal.
During the byte program cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte program
cycle can be CE controlled or WE controlled.
Command Sequence
The V29LC51001 does not provide the “reset”
feature to return the chip to its normal state when
an incomplete command sequence or an
interruption has happened. In this case, normal
operation (Read Mode) can be restored by issuing
a “non-existent” command sequence, for example
Address: 5555H, Data FFH.
Sector Erase Cycle
The V29LC51001 features a sector erase
operation which allows each sector to be erased
and reprogrammed without affecting data stored in
other sectors. Sector erase operation is initiated by
using a specific six-bus-cycle sequence: Two
unlock program cycles, a setup command, two
additional unlock program cycles, and the sector
erase command (see Table 2). A sector must be
first erased before it can be reprogrammed. While
in the internal erase mode, the device ignores any
program attempt into the device. Sector erase is
completed in 10ms max. The V29LC51001 is
shipped with pre-erased sectors (all bits = 1).
Byte Program Cycle
The V29LC51001 is programmed on a byte-by-
byte basis. The byte program operation is initiated
by using a specific four-bus-cycle sequence: two
unlock program cycles, a program setup command
and program data program cycles (see Table 2).
Table 1. Operation Modes Decoding
Decoding Mode
Read
Byte Write
Standby
Output Disable
CE
V
IL
V
IL
V
IH
V
IL
OE
V
IL
V
IH
X
V
IH
WE
V
IH
V
IL
X
V
IH
A
0
A
0
A
0
X
X
A
1
A
1
A
1
X
X
A
9
A
9
A
9
X
X
I/O
READ
PD
HIGH-Z
HIGH-Z
NOTES:
1. X = Don’t Care, V
IH
= HIGH, V
IL
= LOW. V
H
= 12.5V Max.
2. PD: The data at the byte address to be programmed.
V29LC51001 Rev. 0.5 October 2000
8