欢迎访问ic37.com |
会员登录 免费注册
发布采购

M38223M4525FP 参数 Datasheet PDF下载

M38223M4525FP图片预览
型号: M38223M4525FP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS微机 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 78 页 / 980 K
品牌: MITSUBISHI [ Mitsubishi Group ]
 浏览型号M38223M4525FP的Datasheet PDF文件第48页浏览型号M38223M4525FP的Datasheet PDF文件第49页浏览型号M38223M4525FP的Datasheet PDF文件第50页浏览型号M38223M4525FP的Datasheet PDF文件第51页浏览型号M38223M4525FP的Datasheet PDF文件第53页浏览型号M38223M4525FP的Datasheet PDF文件第54页浏览型号M38223M4525FP的Datasheet PDF文件第55页浏览型号M38223M4525FP的Datasheet PDF文件第56页  
MITSUBISHI MICROCOMPUTERS  
3822 Group  
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER  
Table 21 Timing requirements 1 (Standard, One Time PROM version)  
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = 20 to 85 °C, unless otherwise noted)  
Limits  
Unit  
Symbol  
Parameter  
Min.  
2
Typ.  
Max.  
tw(RESET)  
tc(XIN)  
Reset input Lpulse width  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Main clock input cycle time (XIN input)  
Main clock input Hpulse width  
Main clock input Lpulse width  
CNTR0, CNTR1 input cycle time  
CNTR0, CNTR1 input Hpulse width  
CNTR0, CNTR1 input Lpulse width  
INT0 to INT3 input Hpulse width  
INT0 to INT3 input Lpulse width  
125  
45  
twH(XIN)  
twL(XIN)  
40  
tc(CNTR)  
twH(CNTR)  
twL(CNTR)  
twH(INT)  
twL(INT)  
tc(SCLK)  
250  
105  
105  
80  
80  
Serial I/O clock input cycle time (Note)  
Serial I/O clock input Hpulse width (Note)  
Serial I/O clock input Lpulse width (Note)  
Serial I/O input set up time  
800  
370  
370  
220  
100  
twH(SCLK)  
twL(SCLK)  
t
su(RXDSCLK)  
th(SCLKRXD) Serial I/O input hold time  
Note: When bit 6 of address 001A16 is 1(clock synchronous).  
Divide this value by four when bit 6 of address 001A16 is 0(UART).  
Table 22 Timing requirements 2 (Standard, One Time PROM version)  
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = 20 to 85 °C, unless otherwise noted)  
Limits  
Symbol  
Parameter  
Unit  
Min.  
2
Typ.  
Max.  
tw(RESET)  
tc(XIN)  
Reset input Lpulse width  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Main clock input cycle time (XIN input)  
Main clock input Hpulse width  
Main clock input Lpulse width  
CNTR0, CNTR1 input cycle time  
CNTR0, CNTR1 input Hpulse width  
CNTR0, CNTR1 input Lpulse width  
INT0 to INT3 input Hpulse width  
INT0 to INT3 input Lpulse width  
125  
45  
twH(XIN)  
twL(XIN)  
40  
tc(CNTR)  
twH(CNTR)  
twL(CNTR)  
twH(INT)  
twL(INT)  
tc(SCLK)  
500/(VCC-2)  
250/(VCC-2)-20  
250/(VCC-2)-20  
230  
230  
2000  
950  
950  
400  
200  
Serial I/O clock input cycle time (Note)  
Serial I/O clock input Hpulse width (Note)  
Serial I/O clock input Lpulse width (Note)  
Serial I/O input set up time  
twH(SCLK)  
twL(SCLK)  
t
su(RXDSCLK)  
th(SCLKRXD) Serial I/O input hold time  
Note: When bit 6 of address 001A16 is 1(clock synchronous).  
Divide this value by four when bit 6 of address 001A16 is 0(UART).  
52  
 复制成功!