欢迎访问ic37.com |
会员登录 免费注册
发布采购

M30610ECFP 参数 Datasheet PDF下载

M30610ECFP图片预览
型号: M30610ECFP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 197 页 / 2650 K
品牌: MITSUBISHI [ Mitsubishi Group ]
 浏览型号M30610ECFP的Datasheet PDF文件第54页浏览型号M30610ECFP的Datasheet PDF文件第55页浏览型号M30610ECFP的Datasheet PDF文件第56页浏览型号M30610ECFP的Datasheet PDF文件第57页浏览型号M30610ECFP的Datasheet PDF文件第59页浏览型号M30610ECFP的Datasheet PDF文件第60页浏览型号M30610ECFP的Datasheet PDF文件第61页浏览型号M30610ECFP的Datasheet PDF文件第62页  
Mitsubishi microcomputers  
M16C / 61 Group  
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER  
Precautions for Interrupts  
Clear the interrupt enable flag to “0”  
(Disable interrupt)  
Set the interrupt priority level to level 0  
(Disable INTi interrupt)  
Set the polarity select bit  
Clear the interrupt request bit to “0”  
Set the interrupt priority level to level 1 to 7  
(Enable the accepting of INTi interrupt request)  
Set the interrupt enable flag to “1”  
(Enable interrupt)  
______  
Figure 1.13.12. Switching condition of INT interrupt request  
(5) Rewrite the interrupt control register  
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for  
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after  
the interrupt is disabled. The program examples are described as follow:  
Example 1:  
INT_SWITCH1:  
FCLR  
I
; Disable interrupts.  
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.  
NOP  
NOP  
FSET  
; Four NOP instructions are required when using HOLD function.  
; Enable interrupts.  
I
Example 2:  
INT_SWITCH2:  
FCLR  
I
; Disable interrupts.  
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.  
MOV.W MEM, R0  
; Dummy read.  
; Enable interrupts.  
FSET  
I
Example 3:  
INT_SWITCH3:  
PUSHC FLG  
; Push Flag register onto stack  
; Disable interrupts.  
FCLR  
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.  
POPC FLG ; Enable interrupts.  
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted  
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the  
interrupt control register is rewritten due to effects of the instruction queue.  
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the  
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-  
ated. This will depend on the instruction. If this creates problems, use the below instructions to change  
the register.  
Instructions : AND, OR, BCLR, BSET  
58  
 复制成功!