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M30610ECFP 参数 Datasheet PDF下载

M30610ECFP图片预览
型号: M30610ECFP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 197 页 / 2650 K
品牌: MITSUBISHI [ Mitsubishi Group ]
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Mitsubishi microcomputers  
M16C / 61 Group  
Watchdog Timer  
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER  
Watchdog Timer  
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is  
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog  
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the  
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by  
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7  
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu-  
lated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.  
With XIN chosen for BCLK  
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)  
Watchdog timer period =  
BCLK  
With XCIN chosen for BCLK  
pre-scaler dividing ratio (2) X watchdog timer count (32768)  
Watchdog timer period =  
BCLK  
For example, suppose that BCLK runs at 10 MHZ and that 16 has been chosen for the dividing ratio of the  
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.  
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when  
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is  
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by  
writing to the watchdog timer start register (address 000E16).  
Figure 1.14.1 shows the block diagram of the watchdog timer. Figure 1.14.2 shows the watchdog timer-  
related registers.  
Prescaler  
“CM07 = 0”  
“WDC7 = 0”  
1/16  
“CM07 = 0”  
“WDC7 = 1”  
BCLK  
HOLD  
Watchdog timer  
interrupt request  
1/128  
1/2  
Watchdog timer  
“CM07 = 1”  
Write to the watchdog timer  
start register  
Set to  
“7FFF16  
(address 000E16  
)
RESET  
Figure 1.14.1. Block diagram of watchdog timer  
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