Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
INT2
INT0
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
Priority of peripheral I/O interrupts
(if priority levels are same)
UART2 reception
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission
Key input interrupt
DMA0
Low
Processor interrupt priority level (IPL)
Interrupt
request
Interrupt enable flag (I flag)
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 1.13.9. Maskable interrupts priorities (peripheral I/O interrupts)
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