PDSP16256
Control Register
The control register is double buffered. This allows
the writing of a new control word without affecting the
current operation of the device. To activate the new
control register after it has been written to the device
the bank swap signal must be toggled. After a reset
the active control register is loaded directly and bank
swap need not be used.
The internal operation of the PDSP16256 is
controlled by the status of a 16-bit control register. In
the dual filter modes both networks are controlled by
the same register. The significance of the various
bits are shown in Table 6. Tables 7 and 8 define the
control register bit interdependence for the filter and
bank swapping modes.
Control
Register
Function
Bits
15
4
0
0
1
0
1
X
Two independent filters
Two filters in cascade
Single Filter
Bits Decode
Function
Dual filter mode
15
0
Table 7 Control register filter mode bits
15
1
Single filter mode
14:13
14:13
14:13
00
01
10
Sample rate is the system clock
Sample rate is half the system clock
Sample rate is quarter the system
clock
Control
Register
Function
Bits
14:13
12
11
0
Sample rate is eighth the system clock
Output rate equals the input rate
Decimate-by-two
7
6
5
12
1
0
1
1
X
X
0
1
X
0
0
0
1
Control by input pin
11:10
11:10
11:10
11:10
9:8
7
00
01
10
11
00
0
Intermediate device
Lower bank selected
Upper bank selected
Swap on every sample clock
Interface device
Termination device
Single device
Table 8 Control register bank swap bits
These bits MUST be at logical zero
Bank swap is controlled by input pin
Bank swap is controlled by Bit 6
Lower bank if bit 7 is set
Upper bank if bit 7 is set
This bit must be at logical zero
Two independent filters
7
1
6
0
6
1
5
4
0
1
4
Two filters in cascade
3:0
These bits MUST be at logical zero
Table 6 Control register bit allocation
19
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