PDSP16256
DEVICE RESET
1
2
3
4
5
6
7
16 17
37
38
39
SCLK
RES
BUSY
RES must be held low
for 16 cycles
BUSY goes active
Coefficient loading may start
once BUSY has returned low
BYTE WIDE COEFFICIENT LOAD
1
2
3
4
5
6
7
8
67
68
69
70
71
SCLK
CCS
A7:0
00
00
01
00
10
01
00
02
20
03
00
3E
3F
AC
00
02
C15:0
CS
WEN
Control register loaded Blank cycles Coefficients loaded into the required address location. CS must be maintained
with CCS high This example uses byte wide loading (BYTE held low). for two cycles
WORD WIDE COEFFICIENT LOAD
1
2
3
4
5
6
7
8
34
35
36
37
38
SCLK
CCS
A7:0
00
00
01
02
03
04
1E
1F
AC00
0010 0020 0030 0040 0050
001F 0200
C15:0
CS
WEN
Control register loaded Blank cycles Coefficients loaded into the required address location.
with CCS high This example uses word wide loading (BYTE held high).
START OF FILTER OPERATION
1
2
3
4
5
6
7
8
9
16
17
18
19
SCLK
FEN
DA15:0
0010
0020
0030
0040
0050
0090
00A0
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0001 0001 0004 0004
F31:0
CLKOP
The first data sample
is read as FEN goes high
The first result available. CLKOP
indicates the first active result cycle
Figure. 19 Device startup timing diagrams
18
MITEL [ MITEL NETWORKS CORPORATION ]
