Advance Information
MT9300
Interrupt FIFO Register
Read Address:
410 (Read only)
H
7
6
5
4
3
2
1
0
IRQ
0
0
I4
I3
I2
I1
I0
Reset Value:
00 .
H
Bit
Name
Description
7
IRQ
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt
FIFO register is read.
Logic Low indicates that no interrupt is pending and the FIFO is empty.
6:5
4:0
0
Unused bits. Always zero
I<4:0>
I<4:0> binary code indicates the channel number at which a Tone Detector state
change has occurred.
Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Test Register
Read/Write Address: 411
H
7
6
5
4
3
2
1
0
res
res
res
res
res
res
res
Tirq
Reset Value:
Description
00 .
H
Bit
Name
7:1
0
res
Reserved bits. Must always be set to zero for normal operation.
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine.
When high, any change to MTDBI and MTDAI bits of the Main Control Register will
cause an interrupt and its corresponding channel number will be available from the
Interrupt FIFO Register.
When low, normal operation is selected.
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MITEL [ MITEL NETWORKS CORPORATION ]
