Preliminary Information
Pin Description
Pin #
12
13
17
18
22
23
21
24
15, 40, 65, 86
16, 41, 52, 66,
79, 93
Name
TDO
TMS
X1/CLKIN
X2
PLL_LO
PLL_LI
VCO_VSS
VCO_VDD
VDD[0:3]
VSS[0:5]
Description
MT90810
JTAG Serial Output Data
(Output). If not used, this pin should be left
unconnected.
JTAG Mode Control Input
(TTL Input). If not used, this pin should be
left unconnected.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2
(Input). If X1 is clock input, this pin should be
left unconnected.
PLL Loop Filter Output.
(Output 6mA drive).
PLL Loop Filter Input.
(1
µA
Low level/High level Input current).
Ground for On-chip VCO.
+5 Volt Power Supply for On-chip VCO.
+5 Volt Power Supply.
Ground.
Device Overview
Mitel’s MT90810 is a MVIP compliant device. It
provides a complete, cost effective, MVIP compliant
interface between the MVIP Bus and a wide variety
of processors, telephony interfaces and other
circuits. The FMIC supports 384 full duplex, time
division multiplexed (TDM), channels. These
channels are divided into 256 full duplex MVIP
channels and 128 full duplex local channels. The
sample rate for each channel is 8kHz and the width
of each channel is 8 bits for a total data rate of
64kbits/s per channel.
The FMIC’s internal clock circuitry includes both an
analog and a digital PLL and supports all MVIP clock
modes. The device can be configured as a timing
master whereby an external 16.384MHz crystal or
4.096, 8.192 or 16.384MHz external clock source is
used to generate MVIP clock signals. The device can
also operate as a slave to the MVIP bus,
synchronizing its master clock to the MVIP 4MHz
bus clock.
The device’s local serial interface supports PCM
rates of 2.048, 4.096 and 8.192Mb/s, per channel
message mode, an additional control stream, as well
as parallel DMA through the microprocessor port.
Furthermore, the FMIC’s programmable group of
output framing signals and local output clocks may
be used to provide the appropriate frame and clock
pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and
writing of the data memory, connection memory and
all internal control registers. The Connection and
Data memory can be read and updated while the
MVIP bus is active, that is, connections can be made
without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any
input channel to any output channel. This is
accomplished by buffering a single sample of each
channel in an on-chip 384 byte static RAM. Samples
are written into this data RAM in a fixed order and
read out in an order determined by the programming
of the connection memory. An input shift register and
holding latch for each input stream make up the
serial to parallel conversion blocks on the input of
the FMIC and an output holding register an shift
register make up the parallel to serial conversion
blocks on the output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which
provides one sample of buffering for each of the 384
channels. An input shift register and holding latch for
each input stream make up the serial to parallel
conversion blocks on the input. Each input channel is
mapped to a unique location in the RAM, as shown
Table 18 - “Data Memory Mapping”.
Data memory can be read and written by the
microprocessor (See “Software Control” for further
details). Note that writing to data memory may be
futile since the contents will be overwritten by
incoming data on the serial input streams.
2-149
MITEL [ MITEL NETWORKS CORPORATION ]
