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MT90863AL1 参数 Datasheet PDF下载

MT90863AL1图片预览
型号: MT90863AL1
PDF下载: 下载PDF文件 查看货源
内容描述: 3V速率转换数字开关 [3V Rate Conversion Digital Switch]
分类和应用: 开关电信集成电路
文件页数/大小: 35 页 / 156 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT90863  
Advance Information  
the frame alignment register (FAR), users can select  
one of the twenty-four frame evaluation inputs for the  
frame alignment measurement.  
delay to ensure minimum delay between input and  
output data. In wideband data applications, select  
constant throughput delay to maintain the frame  
integrity of the information through the switch.  
A measurement cycle is started by setting the start  
frame evaluation (SFE) bit low for at least one frame.  
Then the evaluation starts when the SFE bit in the  
Internal Mode Selection (IMS) register is changed  
from low to high. One frame later, the complete  
frame evaluation (CFE) bit of the frame alignment  
register changes from low to high to signal that a  
valid offset measurement is ready to be read from  
bits 0 to 9 of the FAR register. The SFE bit must be  
set to zero before a new measurement cycle is  
started.  
The delay through the device varies according to the  
type of throughput delay selected in the LV/C and  
BV/C bits of the local and backplane connection  
memory as described in Table 16 and Table 19.  
Variable Delay Mode (LV/C or BV/C bit = 0)  
The delay in this mode is dependent only on the  
combination of source and destination channels and  
is independent of input and output streams.  
Constant Delay Mode (LV/C bit or BV/C= 1)  
The falling edge of the frame measurement signal  
(FEi) is evaluated against the falling edge of the  
frame pulse (F0i). Table 8 and Figure 8 describe the  
frame alignment register.  
In this mode a multiple data memory buffer is used  
to maintain frame integrity in all switching  
configurations.  
Microprocessor Interface  
Memory Block Programming  
The MT90863 has two connection memories: the  
backplane connection memory and the local  
connection memory. The local connection memory is  
partitioned into high and low parts. The IMS register  
provides users with the capability of initializing the  
local connection memory low and the backplane  
connection memory in two frames. Bit 11 to bit 13 of  
every backplane connection memory location will be  
programmed with the pattern stored in bit 7 to bit 9 of  
the IMS register. Bit 12 to 15 of every local  
connection memory low location will be programmed  
with the pattern stored in bits 3 to 6 of the IMS  
register.  
The MT90863 provides a parallel microprocessor  
interface for non-multiplexed bus structures. This  
interface is compatible with Motorola non-multiplexed  
buses. The required microprocessor signals are the  
16-bit data bus (D0-D15), 8-bit address bus (A0-A7)  
and 4 control lines (CS, DS, R/W and DTA). See  
Figure 16 for Motorola non-multiplexed bus timing.  
The MT90863 microprocessor port provides access  
to the internal registers, connection and data  
memories. All locations provide read/write access  
except for the Data Memory and the Data Read  
Register which are read only.  
The block programming mode is enabled by setting  
the memory block program (MBP) bit of the control  
register high. When the block programming enable  
(BPE) bit of the IMS register is set to high, the block  
programming data will be loaded into bits 11 to 13 of  
every backplane connection memory and bits 12 to  
15 of every local connection memory low. The other  
connection memory bits are loaded with zeros. When  
the memory block programming is complete, the  
device resets the BPE bit to zero. See Figure 7 for  
the connection memory contents when the device is  
in block programming mode.  
Memory Mapping  
The address bus on the microprocessor interface  
selects the internal registers and memories of the  
MT90863. If the A7 address input is low, then the  
registers are addressed by A6 to A0 as shown in  
Table 4.  
If the A7 is high, the remaining address input lines  
are used to select the serial input or output data  
streams corresponding to the subsection of memory  
positions. For data memory reads, the serial inputs  
are selected. For connection memory writes, the  
serial outputs are selected.  
Delay Through the MT90863  
The switching of information from the input serial  
streams to the output serial streams results in a  
throughput delay. The device can be programmed to  
perform time-slot interchange functions with different  
throughput delay capabilities on a per-channel basis.  
For voice applications, select variable throughput  
The control, device mode selection and internal  
mode selection registers control all the major  
functions of the device. The device mode selection  
register and internal mode selection register should  
be programmed immediately after system power-up  
10  
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