MT90863
Advance Information
register. After several master clock cycles, the CDA
bit in the ABR register changes from low to high to
signal the completion of data transfer and resets the
RS bit to low. Read the DRR register to obtain the
data transferred from the memory. Repeat the above
steps for subsequent memory read operations.
Disable the address buffer read operation by setting
the AB bit to low.
bits) of the local connection memory low bits are
transferred to the STo pins.
When sub-rate switching is enabled, the LSR0-1 bits
in the local connection memory high define which bit
position contains the sub-rate data.
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic to
indicate (to the CPU) that a data bus transfer is
complete. When the bus cycle ends, this pin drives
HIGH and then switches to the high-impedance
state. If a short or signal contention prevents the DTA
pin from reaching a valid logic HIGH, it will continue
to drive for approximately 15nsec before switching to
the high-impedance state.
Backplane Connection Memory Control
The backplane connection memory controls the
switching configuration of the backplane interface.
Locations in the backplane connection memory are
associated with particular STio output streams.
The BV/C (Variable/Constant Delay) bit of each
backplane connection memory location allows the
per-channel selection between variable and constant
throughput delay modes for all STio channels.
Initialization of the MT90863
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90863
is in the normal operation mode. A 5KΩ pull-down
resistor can be connected to this pin so that the
device will not enter the JTAG test mode during
power up.
In message mode, the message channel (BMC) bit
of the backplane connection memory enables (if
high) an associated STio output channel. If the BMC
bit is low, the contents of the backplane connection
memory stream address bit (BSAB) and channel
address bit (BCAB) defines the source information
(stream and channel) of the time-slot that will be
switched to the STio streams. When message mode
is enabled, only the lower half (8 least significant
bits) of the backplane connection memory is
transferred to the STio pins.
After power up, the contents of the connection
memory can be in any state. The ODE pin should be
held low after power up to keep all serial outputs in a
high impedance state until the microprocessor has
initialized the switching matrix. This procedure
prevents two serial outputs from driving the same
stream simultaneously.
Local Connection Memory Control
The local connection memory controls the local
interface switching configuration. Local connection
memory is split into high and low parts. Locations in
local connection memory are associated with
particular STo output streams.
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the switch. The memory block
programming feature can also be used to quickly
initialize the DC and OE bit in the backplane and
local connection memory respectively.
The L/B (Local/Backplane Select) bit of each local
connection memory location allows per-channel
selection of source streams from local or backplane
interface.
When this process is complete, the microprocessor
controlling the matrices can either bring the ODE pin
high or enable the OSB bit in IMS register to
relinquish the high impedance state control.
The LV/C (Variable/Constant Delay) bit of each local
connection memory location allows the per-channel
selection between variable and constant throughput
delay modes for all STo channels.
In message mode, the local connection memory
message channel (LMC) bit enables (if high) an
associated STo output channel. If the LMC bit is low,
the contents of the stream address bit (LSAB) and
the channel address bit (LCAB) of the local
connection memory defines the source information
(stream and channel) of the time-slot that will be
switched to the STo streams. When message mode
is enabled, only the lower half (8 least significant
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