欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT90863AL1 参数 Datasheet PDF下载

MT90863AL1图片预览
型号: MT90863AL1
PDF下载: 下载PDF文件 查看货源
内容描述: 3V速率转换数字开关 [3V Rate Conversion Digital Switch]
分类和应用: 开关电信集成电路
文件页数/大小: 35 页 / 156 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号MT90863AL1的Datasheet PDF文件第7页浏览型号MT90863AL1的Datasheet PDF文件第8页浏览型号MT90863AL1的Datasheet PDF文件第9页浏览型号MT90863AL1的Datasheet PDF文件第10页浏览型号MT90863AL1的Datasheet PDF文件第12页浏览型号MT90863AL1的Datasheet PDF文件第13页浏览型号MT90863AL1的Datasheet PDF文件第14页浏览型号MT90863AL1的Datasheet PDF文件第15页  
Advance Information  
MT90863  
15  
0
14  
0
13  
12  
11  
10  
0
9
0
8
0
7
0
6
5
4
3
2
1
0
BBPD BBPD BBPD  
2
0
0
0
0
0
0
0
1
0
Backplane Connection Memory (BCM)  
15  
14  
13  
12  
11  
0
10  
0
9
0
8
0
7
0
6
5
4
3
2
1
0
LBPD  
3
LBPD LBPD  
2
LBPD  
0
0
0
0
0
0
0
0
1
Local Connection Memory Low (LCML)  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
0
7
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Local Connection Memory High (LCMH)  
Figure 7 - Block Programming Data in the Connection Memories  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Location  
Control Register, CR  
(Note 1)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Device Mode Selection Register, DMS  
Internal Mode Selection Register, IMS  
Frame Alignment Register, FAR  
Input Offset Selection Register 0, DOS0  
Input Offset Selection Register 1, DOS1  
Input Offset Selection Register 2, DOS2  
Input Offset Selection Register 3, DOS3  
Input Offset Selection Register 4, DOS4  
Input Offset Selection Register 5, DOS5  
Frame Output Offset Register, FOR0  
Frame Output Offset Register, FOR1  
Address Buffer Register, ABR  
Data Write Register, DWR  
Data Read Register, DRR  
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 0  
Ch 1  
.
Ch 30  
Ch 31  
(Note 2)  
(Note 3)  
1
1
.
1
1
0
0
.
1
1
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32  
Ch 33  
.
Ch 126  
Ch 127  
Notes:  
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.  
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.  
3. Channels 0 to 127 are used when serial stream is at 8Mb/s  
Table 4 - Address Memory Map  
11  
 复制成功!