MT90863
Advance Information
to establish the desired switching configuration as
explained in the Frame Alignment Timing and
Switching Configurations sections.
write operation for the microprocessor port. See
Table 6 and following for bit assignments.
The address buffer mode is controlled by the AB bit
in the control register. The targeted memory for data
read/write is selected by the MS0-2 bits in the control
register.
The control register is used to control the switching
operations in the MT90863. It selects the internal
memory locations that specify the input and output
channels selected for switching.
The data write register (DWR) contains the data to
be transferred to the memory. The data read register
(DRR) contains the data transferred from the
memory.
Control register data consists of: the memory block
programming bit (MBP): the memory select bits
(MS0-2); and, the stream address bits (STA0-4). The
memory block programming bit allows users to
program the entire connection memory block, (see
Memory Block Programming section). The memory
select bits control the selection of the connection
memory or the data memory. The stream address
bits define an internal memory subsections
corresponding to serial input or serial output
streams.
The address buffer register (ABR) allow users to
specify the read or write address by programming
the stream address bits (SA0-4) and the channel
address bits (CA0-6). Data transfer from/to the
memory is controlled by the read/write select bits
(RS, WS). The complete data access (CDA) bit
indicates the completion of data transfer between the
memory and DWR or DRR register.
The data in the DMS register consists of the local
and backplane mode selection bits (LMS0-1 and
BMS0-2) to enable various switching modes for local
and backplane interfaces respectively.
Write Operation Using Address Buffer Mode
Enable the address buffer mode by setting the AB bit
from low to high. Program the DWR register with
data to be transferred to memory. Load the ABR
register with proper channel and stream information.
Change the WS bit in the ABR register from low to
high to initiate the data transfer from the DWR
register to the memory. After several master clock
cycles, the CDA bit in the ABR register changes
from low to high to signal the completion of data
transfer and resets the WS bit to low. Repeat the
above steps for subsequent memory write
operations. Disable the address buffer write
operation by setting the AB bit to low.
The data in the IMS register consists of block
programming bits (LBPD0-3 and BBPD0-2), block
programming enable bit (BPE), output standby bit
(OSB) and start frame evaluation bit (SFE). The
block programming enable bit allows users to
program the entire backplane and local connection
memories, (see Memory Block Programming
section). If the ODE pin is low, the OSB bit enables
(if high) or disables (if low) all ST-BUS output drivers.
If the ODE pin is high, the contents of the OSB bit is
ignored and all ST-BUS output drivers are enabled.
Read Operation Using Address Buffer Mode
See Table 5 for the output high impedance control.
Enable the address buffer mode by setting the AB bit
from low to high. Program the ABR register with
proper channel and stream information. Change the
RS bit in the ABR register from low to high to initiate
the data transfer from the memory to the DRR
Address Buffer Mode
The implementation of the address buffer, data read
and data write registers allows faster memory read/
I
OSB bit
STio0-31
Output Driver
Status
STo0-15
Output Driver
Status
DC bit in
Backplane CM
ODE pin
in
OE bit in Local CM
IMS register
Don’t Care
Don’t Care
0
Per Channel
0
Per Channel
High Impedance
High Impedance
0
0
1
0
1
Don’t care
High Impedance
Enable
Don’t care
High Impedance
Enable
1
1
1
1
Don’t care
Enable
Enable
Table 5 -. Output High Impedance Control
12
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