Advanced Information
CMOS MT90826
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Frame pulse width
Sym
Min
Typ
Max
Units
CLK
1
2
3
4
5
6
7
8
9
t
55
5
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FPW
16.384MHz
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
CLK Period
t
FPS
t
10
55
20
20
115
5
FPH
t
70
40
CP
CLK Pulse Width High
t
CH
CLK Pulse Width Low
t
40
CL
Frame pulse width
t
145
8.192MHz
FPW8
Frame Pulse Setup time before CLK falling
Frame Pulse Hold Time from CLK falling
t
FPS8
t
10
110
50
50
-10
FPH8
10 CLK Period
t
150
75
CP8
11 CLK Pulse Width High
12 CLK Pulse Width Low
13 Clock Rise/Fall Time
t
CH8
t
75
CL8
t , t
+10
r
f
AC Electrical Characteristics - Serial Streams for ST-BUS
Characteristic
STi Set-up Time
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
t
0
8
ns
ns
ns
SIS
STi Hold Time
t
SIH
STo Delay - Active to Active
t
8
11
30
43
CL=30pF
CL=200pF
SOD
4
5
Output Driver Enable (ODE) Delay
t
35
ns
ns
RL=1K, CL=200pF, See
Note 1
ODE
STo delay - Active to High-Z
- High-Z to Active
t
35
RL=1K, CL=200pF, See
Note 1
ZD
Note:1. High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
t
FPW
F0i
V
TT
t
t
CH
t
t
t
t
CP
FPS
r
FPH
CL
V
V
V
CLK
(16.384MHz)
HM
TT
LM
t
t
SOD
f
STo
(16Mb/s)
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Bit0
Ch0
Bit7
Ch0
Bit4
Ch0
Bit1
V
TT
t
t
SIH
SIS
STi
(16Mb/s)
Ch0
Bit6
Ch0
Bit5
Ch0
Bit3
Ch0
Bit2
Ch255
Bit1
Ch255
Bit0
Ch0
Bit7
Ch0
Bit4
Ch0
Bit1
V
TT
Figure 6 - ST-BUS Timing for Stream rate of 16.384 Mb/s
23
MITEL [ MITEL NETWORKS CORPORATION ]
