MT90823
CMOS
The MT90823 provides two different interface timing
modes controlled by the WFPS pin. If the WFPS pin
is low, the MT90823 is in ST-BUS/GCI mode. If the
WFPS pin is high, the MT90823 is in the wide frame
pulse (WFP) frame alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse
can be in either ST-BUS or GCI format. The
MT90823 automatically detects the presence of an
input frame pulse and identifies it as either ST-BUS
or GCI. In ST-BUS format, every second falling edge
of the master clock marks a bit boundary and the
data is clocked in on the rising edge of CLK, three
quarters of the way into the bit cell, see Figure 11. In
GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in
on the falling edge of CLK at three quarters of the
way into the bit cell, see Figure 12.
Wide Frame Pulse (WFP) Frame Alignment
Timing
When the device is in WFP frame alignment mode,
the CLK input must be at 16.384 MHz, the FE/HCLK
input is 4.096 MHz and the 8 kHz frame pulse is in
ST-BUS format. The timing relationship between
CLK, HCLK and the frame pulse is defined in Figure
13.
streams. For details on the use of the source
address data (CAB and SAB bits), see Table 13 and
Table 14. Once the source address bits are
programmed by the microprocessor, the contents of
the data memory at the selected address are
transferred to the parallel-to-serial converters and
then onto an ST-BUS output stream.
By having several output channels connected to the
same input source channel, data can be broadcasted
from one input channel to several output channels.
In message mode, the microprocessor writes data to
the connection memory locations corresponding to
the output stream and channel number. The lower
half (8 least significant bits) of the connection
memory content is transferred directly to the
parallel-to-serial converter. This data will be output
on the ST-BUS streams in every frame until the data
is changed by the microprocessor.
The five most significant bits of the connection
memory controls the following for an output channel:
message or connection mode; constant or variable
delay; enables/tristate the ST-BUS output drivers;
and, enables/disable the loopback function. In ad-
dition, one of these bits allows the user to control the
CSTo output.
If an output channel is set to a high-impedance state
through the connection memory, the ST-BUS output
will be in a high impedance state for the duration of
that channel. In addition to the per-channel control,
all channels on the ST-BUS outputs can be placed in
a high impedance state by either pulling the ODE
input pin low or programming the output standby
(OSB) bit in the interface mode selection register to
low. This action overrides the individual per-channel
programming by the connection memory bits.
The connection memory data can be accessed via
the microprocessor interface through the D0 to D15
pins. The addressing of the device internal registers,
data and connection memories is performed through
the address input pins and the Memory Select (MS)
bit of the control register. For details on device
addressing, see Software Control and Control
Register bits description (Tables 4, 6 and 7).
Serial Data Interface Timing
The master clock frequency must always be twice
the data rate. The master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz for serial data rate of
2.048, 4.096 or 8.192 Mb/s respectively. The input
and output stream data rates will always be identical.
When the WFPS pin is high, the frame alignment
evaluation feature is disabled, but the frame input
offset registers may still be programmed to
compensate for the varying frame delays on the
serial input streams.
Switching Configurations
The MT90823 maximum non-blocking switching
configurations is determined by the data rates
selected for the serial inputs and outputs. The
switching configuration is selected by two DR bits in
the IMS register. See Table 8 and Table 9.
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the
device is configured with 16-input/16-output data
streams each having 32 64 kb/s channels. This
mode requires a CLK of 4.094 MHz and allows a
maximum non-blocking capacity of 512 x 512
channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the
device is configured with 16-input/16-output data
streams each having 64 64 kb/s channels. This
8
MITEL [ MITEL NETWORKS CORPORATION ]
