MT90823
Pin Description
CMOS
Pin #
84
100
PLCC MQFP
1, 11, 31, 41,
30, 54 56, 66,
64, 75 76, 99
100
LQFP
28,
38,
53,
63,
73,
96
37,
64,98
120
BGA
A1,A2,A12,A13,
B1,B2,B7,B12,
B13,C3,C5,C7,
C9,C11,E3,E11
G3,G11,J3,J11,
L3,L5,L7,L9,L11,
M2,M12,M13,N1
C4,C6,C8,C10,
D3,D11,F3,F11,
H3,H11,K3,K11,
L4,L6,L8,L10
B6,A6,A5,B5,A4,
B4,A3,B3
Name
Description
V
SS
Ground.
2, 32,
63
5, 40,
67
V
DD
+3.3 Volt Power Supply.
3 - 10
68-75
65 -
72
STo8 - 15
ST-BUS Output 8 to 15 (5V Tolerant Three-state
Outputs):
Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
STi0 - 15
ST-BUS Input 0 to 15 (5V Tolerant Inputs):
Serial
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
F0i
Frame Pulse (5V Tolerant Input):
When the WFPS
pin is low, this input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS and GCI specifications. When the
WFPS pin is high, this pin accepts a negative frame
pulse which conforms to WFPS formats.
12 -
27
81-96
78 -
93
C1,C2,D1,D2,E1,
E2,F1,F2,G1,G2,
H1,H2,J1,J2,K1,
K2
L1
28
97
94
29
98
95
L2
FE/HCLK
Frame Evaluation / HCLK Clock (5V Tolerant Input):
When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame alignment
in the wide frame pulse (WFP) mode.
CLK
Clock (5V Tolerant Input):
Serial clock for shifting data
in/out on the serial streams (STi/o 0 - 15). Depending
upon the value programmed at bits DR0 - 1 in the IMS
register, this input accepts a 4.096, 8.192 or 16.384
MHz clock.
Test Mode Select (3.3V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
Test Serial Data In (3.3V Tolerant Input with internal
pull-up):
JTAG serial test instructions and data are
shifted in on this pin.
Test Serial Data Out (3.3V Output):
JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
31
100
97
N1
33
6
3
N2
TMS
34
7
4
M3
TDI
35
8
5
N3
TDO
4
MITEL [ MITEL NETWORKS CORPORATION ]
