CMOS
For multiplexed operation, the 8-bit data and address
(AD0-AD7), 8-bit Data (D8-D15), Address strobe/
Address latch enable (AS/ALE), Data strobe/Read
(DS/RD), Read/Write /Write (R/W / WR), Chip select
(CS) and Data transfer acknowledge (DTA) signals
are required. See Figure 13 and Figure 14 for
multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the 16-bit data
bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7)
and 4 control lines (CS, DS, R/W and DTA) signals
are required. See Figure 15 for Motorola non-
multiplexed microport timing.
The MT90823 microport provides access to the
internal registers, connection and data memories. All
locations provide read/write access except for the
data memory and the frame alignment register which
are read only.
Memory Mapping
The address bus on the microprocessor interface
selects the MT90823 internal registers and memory.
If the A7 address input is low, then the control (CR),
interface mode selection (IMS), frame alignment
(FAR) and frame input offset (FOR) registers are
addressed by A6 to A0 as shown in Table 4.
If the A7 address input is high, then the remaining
address input lines are used to select up to 128
memory subsection locations. The number selected
corresponds to the maximum number of channels
per input or output stream. The address input lines
and the stream address bits (STA) of the control
register allow access to the entire data and
connection memories.
The control and IMS registers together control all the
major functions of the device. The IMS register
should be programmed immediately after system
power-up to establish the desired switching
configuration (see “Serial Data Interface Timing”
and “Switching Configurations” ).
The control register controls switching operations in
the MT90823. It selects the internal memory
locations that specify the input and output channels
selected for switching.
The data in the control register consists of the
memory block programming bit (MBP), the memory
select bit (MS) and the stream address bits (STA).
The memory block programming bit allows users to
program the entire connection memory block, (see
“Memory Block Programming” ). The memory select
bit controls the selection of the connection memory
or the data Memory. The stream address bits define
MT90823
an internal memory subsections corresponding to
input or output ST-BUS streams.
The data in the IMS register consists of block
programming bits (BPD0-BPD4), block programming
enable bit (BPE), output standby bit (OSB), start
frame evaluation bit (SFE) and data rate selection
bits (DR0, DR1). The block programming and the
block programming enable bits allows users to
program the entire connection memory, (see Memory
Block Programming section). If the ODE pin is low,
the OSB bit enables (if high) or disables (if low) all
ST-BUS output drivers. If the ODE pin is high, the
contents of the OSB bit is ignored and all ST-BUS
output drivers are enabled.
Connection Memory Control
The contents of the CSTo bit of each connection
memory location are output on the CSTo pin once
every frame. The CSTo pin is a 4.096, 8.192 or
16.384 Mb/s output carrying 512, 1,024 or 2,048 bits
respectively. If the CSTo bit is set high, the
corresponding bit on the CSTo output is transmitted
high. If the CSTo bit is low, the corresponding bit on
the CSTo output is transmitted low. The contents of
the CSTo bits of the connection memory are
transmitted sequentially via the CSTo pin and are
synchronous with the data rates on the other ST-BUS
streams.
The CSTo bit is output one channel before the
corresponding channel on the ST-BUS. For example,
in 2Mb/s mode, the contents of the CSTo bit in
position 0 (STo0, CH0) of the connection memory is
output on the first clock cycle of channel 31 via CSTo
pin. The contents of the CSTo bit in position 32
(STo1, CH0) of the connection memory is output on
the second clock cycle of channel 31 via CSTo pin.
When either the ODE pin or the OSB bit is high, the
OE bit of each connection memory location enables
(if high) or disables (if low) the output drivers for an
individual ST-BUS output stream and channel. Table
5 details this function.
The connection memory message channel (MC) bit
(if high) enables message mode in the associated
ST-BUS output channel. When message mode is
enabled, only the lower half (8 least significant bits)
of the connection memory is transferred to the
ST-BUS outputs.
If the MC bit is low, the contents of the connection
memory stream address bit (SAB) and channel
address bit (CAB) defines the source information
(stream and channel) of the time-slot that will be
switched to the output.
11
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