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MT9076 参数 Datasheet PDF下载

MT9076图片预览
型号: MT9076
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1 3.3V单芯片收发器 [T1/E1/J1 3.3V Single Chip Transceiver]
分类和应用:
文件页数/大小: 160 页 / 413 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9076  
Preliminary Information  
Bit  
Name  
Functional Description  
Reserved. Must be kept at 0 for normal operation.  
7
6
- -  
TE  
Transmit E bits. When zero and CRC-4 synchronization is achieved, the E-bits transmit the  
received CRC-4 comparison results to the distant end of the link, as per G.703. That is,  
when zero and CRC-4 synchronization is lost, the transmit E-bits will be zero. If one, and  
CRC-4 synchronization is lost the transmit E-bits will be one.  
5
4
3
TAIS16 Transmit AIS Time Slot 16. If one, an all ones signal is transmitted in time slot 16. If zero,  
time slot functions normally.  
TxAO  
Einv  
Transmit All Ones. When low, this control bit forces a framed or unframed (depending on  
the state of Transmit Alarm Control bit 0) all ones to be transmit at TTIP and TRING.  
Ebit Error Inversion. When zero, received Ebits set to zero are counted in the Ebit error  
counter and interrupt generator. When one, Ebits set to one are counted in the Ebit error  
counter and interrupt generator.  
2-0  
- - -  
Unused  
Table 88 - Transmit Alarm Control Word (E1)  
(Page 1, Address 11H)  
Bit  
Name  
Functional Description  
7
6
5
- - -  
- - -  
Unused.  
Unused.  
EXZ  
Excess Zeros. Setting this bit causes each occurance of received excess zeros to  
increment the Line Code Violation Counter. Excess zeros are defined as 4 or more  
successive zeros for HDB3 encoded data, or 16 or more successive zeros for non-HDB3  
encoded data.  
4
3
SaBorNi Sa Bit or Nibble. Set this bit to determine the criteria for interrupts due to transitions of Sa  
bits. If set to one, a change of state of any Sa bit is the criteria. If set to zero, a change of  
state of an Sa nibble is the criteria. Note that the selected event can only trigger an interrupt  
if the interrupt mask bit SaIM is set high in the Interrupt Mask Word Two - page 1 address  
1DH bit 0.  
RxTRSP Receive Transparent Mode. When this bit is set to one, the framing function is disabled on  
the receive side. Data coming from the receive line passes through the slip buffer and drives  
DSTo with an arbitrary alignment. When zero, the receive framing function operates  
normally.  
2
1
TxTRSP Transmit Transparent Mode. If one, the MT9076 is in transmit transparent mode. No  
framing or signaling is imposed on the data transmit from DSTi onto the line. If zero, it is in  
termination mode.  
TIU1  
Transmit International Use One. When CRC-4 operation is disabled (CSYN=1), this bit is  
transmit on the PCM 30 2048 kbit/sec. link in bit position one of time-slot zero of non-frame-  
alignment frames. It is reserved for international use and should normally be kept at one. If  
CRC processing is used, i.e., CSYN =0, this bit is ignored.  
0
TIU0  
Transmit International Use Zero. When CRC-4 operation is disabled (CSYN=1), this bit is  
transmit on the PCM 30 2048 kbit/sec. link in bit position one of time-slot zero of frame-  
alignment frames. It is reserved for international use and should normally be kept at one. If  
CRC processing is used, i.e., CSYN =0, this bit is ignored.  
Table 89 - TS0 Control Word (E1)  
(Page 1, Address 12H)  
94  
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