Preliminary Information
MT9076
Bit
Name
Functional Description
7
RST
Reset. When this bit is changed from zero to one the device will reset to its default mode.
See the Reset Operation section for the default settings.
6
SPND
INTA
Suspend Interrupts. If one, the IRQ output (pin 12 in PLCC, 85 in MQFP) will be in a
high-impedance state and all interrupts will be ignored. If zero, the IRQ output will function
normally.
5
4
3
Interrupt Acknowledge. A zero-to-one or one-to-zero transition will clear any pending
interrupt and make IRQ high.
CNTCLR Counter Clear. If one, all status counters are cleared and held low. Zero for normal
operation.
SAMPLE One Second Sample. Setting this bit causes the error counters (change of frame
alignment, loss of frame alignment, lcv errors, crc errors, severely errored frame events
and multiframes out of sync) to be updated on one second intervals coincident with the
one second timer (status page 3 address 12H bit 7).
2
OOFP
Out of Frame Pause. If set high, this bit will suspend operation of the Line Code VIolation
Counter during an out - of - frame condition; upon achieving terminal frame
synchronization the counter will resume normal operation. If set low, the Line Code
Violation counter will continue to count errors even if terminal frame synchronization is
lost.
1
0
- -
Reserved. Set low for normal operation.
D20
Double 20. Set low for normal operation. Set high to double clock speed in the HDLC to
speed up memory accesses from 160ns between consecutive reads/writes to 80ns
between consecutive reads/writes.
Table 97 - Signaling Control Word (E1)
(Page 1, Address 1AH)
99
MITEL [ MITEL NETWORKS CORPORATION ]
