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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
Bit  
Name  
Functional Description  
Bit  
Name  
Functional Description  
3
BPVIM  
Bipolar Violation Interrupt  
Mask. When unmasked an  
interrupt is initiated whenever a  
5
OOFOM  
Out Of Frame Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
is initiated whenever the out  
of frame counter changes  
state from changes from  
FFH to 00H. If 1 - unmasked,  
0 - masked.  
bipolar  
violation  
(excluding  
B8ZS encoding) is encountered.  
If 1- unmasked, 0 - masked.  
2
PRBSIM Psuedo  
Random  
Error  
Bit  
Interrupt  
Sequence  
Mask. When unmasked an  
interrupt will be generated upon  
detection of an error with a  
channel selected for PRBS  
testing. 1 - unmasked, 0 -  
masked.  
4
COFAOM  
Change  
Alignment  
of  
Frame  
Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
is initiated whenever the  
change of frame alignment  
counter changes from FFH  
to 00H. If 1 - unmasked, 0 -  
masked.  
1
PDVIM  
Pulse  
Density  
Mask.  
an  
Violation  
Interrupt  
unmasked  
When  
interrupt  
is  
triggered whenever a sequence  
of excessive consecutive zeros  
is received on the line, or the  
incoming pulse density is less  
than N ones in a time frame of  
8(N+1) where N = 1 to 23. If 1 -  
unmasked, 0 - masked.  
3
2
BPVOM  
Bipolar Violation Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
is initiated whenever the  
bipolar violation counter  
changes from FFH to 00H. If  
1- unmasked, 0 - masked.  
0
- - -  
Unused.  
PRBSOM  
Psuedo  
Random  
Bit  
Sequence Error Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
will be generated whenever  
the PRBS error counter  
changes from FFH to 00H. If  
1 - unmasked, 0 - masked.  
Table 33 - Interrupt Mask Word One (T1)  
(Page 1, Address 1CH  
Bit  
Name  
Functional Description  
7
FEOM  
Framing Bit Error Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
is initiated whenever the  
framing bit error counter  
changes from FFH to 00H. If  
1 - unmasked, 0 - masked.  
1
PRBSMFOM Psuedo  
Sequence  
Random  
Bit  
Multiframe  
Overflow  
Counter  
Interrupt  
Mask.  
When  
unmasked an interrupt will  
be generated whenever the  
multiframe counter attached  
to the PRBS error counter  
overflows. FFH to 00H. If 1 -  
unmasked, 0 - masked.  
6
CRCOM  
CRC-6  
Error  
Counter  
Overflow Interrupt Mask.  
When unmasked an interrupt  
is initiated whenever the  
CRC-6  
error  
counter  
changes from FFH to 00H. If  
1 - unmasked, 0 - masked.  
0
MFOOFOM  
Multiframes Out Of Sync  
Overflow Interrupt Mask.  
When unmasked an interrupt  
will be generated when the  
multiframes out of frame  
counter changes from FFH  
to 00H. If 1 - unmasked, 0 -  
masked.  
Table 34 - Interrupt Mask Word Two (T1)  
(Page 1, Address 1DH)  
Table 34 - Interrupt Mask Word Two (T1)  
(Page 1, Address 1DH)  
49  
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