MT9074
Advance Information
Bit
Name
Functional Description
Bit
Name
Functional Description
0
PLBK
Payload Loopback. If one, all
time slots received on RTIP/
RRING are connected to TTIP/
TRING on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. If receive robbed bit
signaling data is to be included in
the looped data, then the control
bit RBEn (Page 1 Address 14H,
Bit 5) must be set low, otherwise
transmit signaling data will be
placed into the LSB of each
timeslot every sixth frame. Setting
all Clear Channel control bits high
(Bit 0 in the Per Time Slot Control
words - Pages 7 and 8 Address
10H to IFH inclusive) has the
same effect as setting control bit
RBEn low.
7
RxB8ZS Receive B8ZS Enable. If one,
receive
B8ZS
decoding
is
enabled.
6
MLBK
Metallic Loopback. If one, then
RRTIP/RRING are connected
directly to TTIP and TRING
respectively. If zero, this feature is
disabled. Set the transmit line
build out to -7.5dB when metallic
loopback is enabled.
5
4
3
TxB8ZS Transmit B8ZS Enable. If one, all
zero octets are substituted with
B8ZS codes.
FBS
Forced Bit Stuffing. If set any
transmit DS0 channel containing
all zeros has bit 7 forced high.
DLBK
Digital Loopback. If one, the
digital stream to the transmit LIU
is looped back in place of the
digital output of the receive LIU.
Data coming out of DSTo will be a
delayed version of DSTi. If zero,
this feature is disabled.
Table 26 - Coding and Loopback Control Word
(T1)(Page 1, Address 15H)
Bit Name
Functional Description
7-0
- - - Unused
2
1
RLBK
SLBK
Remote Loopback. If one, all
time slots received on RRTIP/
RRING are connected to TTIP/
TRING on the DS1 side of the
MT9074. If zero, this feature is
disabled.
Table 27 - Reserved (T1)
(Page 1, Address 16H)
Bit
Name
Functional Description
ST-BUS Loopback. If one, all
time slots of DSTi are connected
to DSTo on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. See Loopbacks section.
7-0 TxSD7-0 Transmit Set Delay Bits 7-0.
Writing to this register forces a one
time setting of the delay through the
transmit slip buffer. Delay is defined
as the time interval between the
write of the transmit STBUS channel
containing DS1 timeslot 1 and its
subsequent read. Delay is modified
by moving the position of the
internally generated DS1 frame
boundary.Delay (when set) will
Table 26 - Coding and Loopback Control Word
(T1)(Page 1, Address 15H)
always be less than
1
frame
(125uS). This register must be
programmed with a non-zero value
(such as 0FH).
Table 28 - Transmit Elastic Buffer Set Delay
Word (T1) (Page 1, Address 17H)
46
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