Advance Information
MT9074
Bit
Name
Functional Description
Unused.
Bit Name
Functional Description
1
0
- - -
7-0 TxM7-0 Transmit Message Bits 7 - 0. The
contents of this register are
transmitted into those outgoing DS1
channels selected by the Per Time
Slot Control registers.
LOS/
LOF
Loss of Signal or Loss of Frame
Selection. If one, pin LOS will go
high when a loss of signal state
exists (criteria as per LLOS status
bit). If low, pin LOS will go high
when either a loss of signal or a
loss of frame alignment state exits.
Table 29 - Transmit Message Word (T1)
(Page 1, Address 18H)
Table 30 - Error Insertion Word (T1)
(Page 1, Address 19H)
Bit
Name
Functional Description
7
BPVE
Bipolar
Violation
Error
Bit
Name
Functional Description
Insertion. A zero-to-one transition
of this bit inserts a single bipolar
violation error into the transmit
DS1 data. A one, zero or one-to-
zero transition has no function.
7
RST
Software reset. Setting this bit is
equivalent to performing
a
hardware reset. All counters are
cleared and the control registers
are set to their default values.
This control bit is internally
cleared after the reset operation
is complete.
6
5
CRCE
FTE
CRC-6 Error Insertion. A zero-to-
one transition of this bit inserts a
single CRC-6 error into the
transmit ESF DS1 data. A one,
zero or one-to-zero transition has
no function.
6
5
SPND
INTA
Suspend Interrupts. If one, the
IRQ output will be in a high-
impedance
state
and
all
Terminal Framing Bit Error
Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit D4 Ft pattern or the
transmit ESF framing bit pattern
(in ESF mode). A one, zero or
one-to-zero transition has no
function.
interrupts will be ignored. If zero,
the IRQ output will function
normally.
Interrupt Acknowledge. Setting
this bit clears all the interrupt
status bits and forces the IRQ pin
into high impedance. The control
bit itself is then internally cleared.
4
FSE
Signal
Framing
Bit
Error
Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit Fs bits (in D4 mode
only). A one, zero or one-to-zero
transition has no function.
4
3
CNTCLR Counter Clear. If one, all status
error counters are cleared and
held low.
SAMPLE One Second Sample. Setting
this bit causes the error counters
(change of frame alignment, loss
of frame alignment, bpv errors,
crc errors, severely errored frame
events and multiframes out of
sync) to be updated on one
second intervals coincident with
the one second timer (status
page 3 address 12H bit 7).
3
2
LOSE
PERR
Loss of Signal Error Insertion. If
one, the MT9074 transmits an all
zeros signal (no pulses). Zero
code suppression is overridden. If
zero, data is transmitted normally.
Payload Error Insertion. A zero -
to - one transition of this bit inserts
a single bit error in the transmit
payload. A one, zero or one-to-
zero transition has no function.
Table 31 - Reset Control Word (T1)
(Page 1, Address 1AH)
Table 30 - Error Insertion Word (T1)
(Page 1, Address 19H)
47
MITEL [ MITEL NETWORKS CORPORATION ]
