欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号MT9074AL的Datasheet PDF文件第39页浏览型号MT9074AL的Datasheet PDF文件第40页浏览型号MT9074AL的Datasheet PDF文件第41页浏览型号MT9074AL的Datasheet PDF文件第42页浏览型号MT9074AL的Datasheet PDF文件第44页浏览型号MT9074AL的Datasheet PDF文件第45页浏览型号MT9074AL的Datasheet PDF文件第46页浏览型号MT9074AL的Datasheet PDF文件第47页  
Advance Information  
MT9074  
Bit  
Name  
Functional Description  
Bit  
Name  
Functional Description  
2
FSI  
Fs Bit Include. Only applicable  
in D4 mode (not ESF or  
SLC96). Setting this bit causes  
errored Fs bits to be included as  
framing bit errors. A bad Fs bit  
will increment the Framing Error  
Bit Counter, and will potentially  
cause a reframe (if it is the  
second bad framing bit out of 5).  
The Fs bit of the receive frame  
12 will only be included if  
D4SECY is set low.  
7
ESF  
Extended  
Setting  
transmission and reception of  
the 24 frame superframe DS1  
protocol.  
Super  
Frame.  
enables  
this  
bit  
6
SLC96  
SLC96 Mode Select. Setting  
this bit enables input and output  
of the Fs bit pattern on the TxDL  
and  
RxDL  
pins.  
Frame  
synchronization is the same as  
in the case of D4 operation. The  
transmitter will insert A and B  
1
0
ReFR  
Reframe. Setting this bit causes  
an automatic reframe.  
bits every  
6
frames after  
synchronizing to the Fs pattern  
clocked into Txdl. Receive Fs  
bits are not monitored for the  
Framing Bit Error Counter.  
MFReFR MultiFrame Reframe. Only  
applicable in D4 or SLC96  
mode. Setting this bit causes an  
automatic multiframe reframe.  
The signalling bits are frozen  
until multiframe synchronization  
is achieved. Terminal frame  
synchronization is not affected.  
5
CXC  
Cross Check. Setting this bit in  
ESF mode enables a cross  
check of the CRC-6 remainder  
before the frame synchronizer  
pulls into sync. This process  
adds at least 6 milliseconds to  
the frame synchronization time.  
Setting this bit in D4 (not ESF)  
mode enables a check of the Fs  
bits in addition to the Ft bits  
during frame synchronization  
Table 21 - Framing Mode Select (T1)  
(Page 1, Address 10H)  
4 - 3  
RS1- 0  
Reframe Select 1 - 0. These  
bits set the criteria for an  
automatic reframe in the event  
of framing bits errors. The  
combinations available are:  
RS1 - 0, RS0 - 0 = sliding  
window of 2 errors out of 4.  
RS1 - 0, RS0 - 1 = sliding  
window of 2 errors out of 5.  
RS1 - 1, RS0 - 0 = sliding  
window of 2 errors out of 6.  
RS1 - 1, RS0 - 1 = no reframes  
due to framing bit errors.  
Table 21 - Framing Mode Select (T1)  
(Page 1, Address 10H)  
43  
 复制成功!