MT90220
AC Electrical Characteristics† - Generic PCM Interface Mode
‡
Characteristic
Sym
Min
Typ
Max
Units
Test Conditions
1
2
TXCK/RXCK Clock period
for T1, 1.544 MHz mode
for E1, 2.048 MHz mode
tcyc
ns
duty cycle 40 / 60%
648
488
TXCK/RXCK Clock Width High or
Low
for T1, 1.544 MHz mode
for E1, 2.048 MHz mode
t
ns
4W
260
195
3
4
5
6
7
8
Frame Pulse Setup
t
4
1
3
0
ns
ns
ns
ns
ns
ns
FPS
Frame Pulse hold
t
FPH
DSTi 0-7 Serial Input Setup
DSTi 0-7 Serial Input Hold
DSTo 0-7 Serial Output Delay
t
SIS
t
SIH
t
25
25
CL = 150pF
CL = 150pF
SOD
TXSYNC/RXSYNC Frame Pulse
delay after TXCK/RXCK active
border
t
FPD
9
TXSYNC when input (PCM Mode 5
& 7) is sampled at the end of the bit
period
t
25ns
.5
FPSi
t
t
cyc
10 TXSYNC when input (PCM Mode 5
& 7) is sampled at the end of the bit
period
t
.5
FPSH
cyc
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V =3.3V, and for design aid only: not guaranteed and not subject to production testing
DD
PCM
Channel 24
LSB Bit
Framing
Bit
Channel 1
MSB Bit
Channel 1
Bit 2
Bit Cells
T1 (1.544 Mbps)
PCM
Bit Cells
E1 (2.048 Mbps)
Channel 31
LSB Bit
Channel 0
MSB Bit
Channel 0
Bit 2
Channel 0
Bit 3
TXSYNC0-7/
RXSYNC0-7
Positive Pulse
BIT Transmitted at
Rising Edge
BIT Sampled at
Falling Edge
TXCK0-7/
RXCK0-7
TXSYNC0-7/
RXSYNC0-7
Negative Pulse
BIT Transmitted at
Falling Edge
BIT Sampled at
Rising Edge
TXCK0-7/
RXCK0-7
Figure 26 - Generic PCM Interface Timing Diagram
(Frame Pulse Location)
88
MITEL [ MITEL NETWORKS CORPORATION ]
