MT90220
Each of these two interrupt sources can be masked
by writing a ’1’ to the bit corresponding to the
interrupt source in the IRQ Link 0 Enable register.
The IRQ IMA Group Overflow Enable register is
used to enable any overflow conditions for a specific
IMA Group. Each of the four bits correspond to one
of the four IMA Groups. A value of ’1’ enables the
report of the overflow condition to the upper IRQ
levels.
6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA
Input UNI Overflow Status Registers
The IRQ Link UNI Overflow and the IRQ UTOPIA
Input UNI Overflow Status registers report the
overflow condition from any of the counters
associated with the TX PCM link, the RX PCM link or
the TX UTOPIA I/F. They also report the overflow
condition from the level of the UTOPIA RX FIFO
when the link is used in UNI mode. The 13 interrupt
sources are organized in the following two registers:
6.2.5 IRQ IMA Overflow Status and RX UTOPIA
IMA Group FIFO Overflow Enable Registers
There are five possible sources of overflow
conditions that can be reported for each of the 4 IMA
Groups.
The IRQ IMA Overflow Status register captures
(latches) the overflow condition from any of the four
counters associated with the UTOPIA TX I/F when
the PCM link is used in IMA mode. It also latches
when an overflow condition occurs in the RX
UTOPIA FIFO associated to a PCM link when in IMA
mode.
•
an 8-bit register that reports the overflow
condition from the eight counters associated
with a TX or RX PCM link (the IRQ Link UNI
Overflow Status registers)
•
a 5-bit register that reports the overflow
condition from the four counters associated with
the UTOPIA TX I/F to the PCM link used in UNI
mode as well as an overflow condition from the
RX UTOPIA FIFO associated to a RX PCM link
when in UNI mode (the IRQ UTOPIA Input UNI
Overflow Status registers)
The status bit is cleared by overwriting it with a 0.
Reading the registers or writing a ’1’ to these
registers will not change the content of the registers.
A counter generates an interrupt request, if not
masked, when the counter overflows (i.e. starts over
from 0 after reaching the maximum counter value -
refer to paragraph 6.1 for more details on the
operation of the counters). An interrupt request can
also be generated, if not masked, when an overflow
condition is detected in the UTOPIA RX FIFO
associated with an IMA Group.
The five bits in the IRQ UTOPIA Input UNI Overflow
Status registers are latched to report an overflow
condition. The status bit is cleared by overwriting it
with a 0. Reading the registers or writing a ’1’ to
these registers will not change the content of the
registers.
There is no enable register directly associated to the
IRQ Link UNI Overflow Status registers. The
source of the interrupt request can be controlled
either by enabling the interrupt from the counters or
from the RX UTOPIA Link FIFO Overflow Enable
register. Refer to 6.1 Counter Block paragraph for
more details on the operation of the counters.
There is one enable register used to enable the
generation of an interrupt by the overflow condition
of the RX UTOPIA FIFO associated with an IMA
Group. This is the RX UTOPIA IMA Group FIFO
Overflow Enable register.
6.3 Register and Memory Map
6.2.4 IRQ IMA Group Overflow Status and Enable
Registers
6.3.1 Access to the Various Registers
There are 20 sources of IMA Group overflow
conditions organized in two levels of registers:
Since the MT90220 and microprocessor operate
from two different clock sources, access to a
MT90220 register is asynchronous. Data is
synchronized between the MT90220 and the
microprocessor using either direct or indirect
(synchronized) methods of access.
•
four low level, 5-bit registers (one register per
IMA Group)
•
one intermediate 4-bit register that is used to
report the overflow conditions for each IMA
Group to minimize the number of accesses to
identify the source of an overflow condition
The direct method is used during a read access
whenever data does not change or data changes do
not represent any problem. There is no register that
clears status bits upon a read access. A write action
is always required to clear a status bit.
The IRQ IMA Group Overflow Status register
indicates which one of the four IMA Groups is
reporting an overflow condition. When enabled, the
bits in this status register reflect any overflow
condition reported by the IRQ IMA Overflow Status
registers.
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