MT90220
6.2.2 IRQ Link Status and IRQ Link Enable
Registers
register to the bit corresponding to the interrupt
source.
There are eight IRQ Link Status and eight IRQ Link
Enable registers; one of each per link. The following
six types of interrupts are reported (in the six least
significant bits of the IRQ Link Status registers) for
each link:
In some situations, an interrupt source can be
masked as part of an interrupt service routine. This
makes it possible to detect further interrupts of
higher priority. For example, if an interrupt for a
counter is received, the source of the interrupt can
be masked by writing 0 to the bit 0 and then starting
a separate process, outside of the Interrupt Service
Routine. The independent process would read,
reload and re-enable the counter to produce another
interrupt service request, if necessary. At the end of
this process, the enable bit in the IRQ Link Enable
register would be set to ’1’ to detect any future
interrupt requests.
•
Bit 5 latched: reports that an ICP Cell with
changes was received on a RX PCM link.
•
Bit 4 latched: reports an IV (ICP Cell violation)
condition on a RX PCM link.
•
Bit 3 latched: reports an LODS (Link is Out of
Delay Synchronization) condition on a RX PCM
link.
•
•
Bit 2 latched: reports an LIF (Loss of IMA
Frame) condition on a RX PCM link.
Bit 1 latched: reports an LCD (Loss of Cell
Delineation) condition on a RX PCM link.
6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ
Link 0 Enable Registers
Bit 0 (LSB) is a status bit. It reports an interrupt for
an overflow condition in one or more of the 12
counters associated with the link. It is also used to
report an overflow condition in the UTOPIA RX FIFO
associated with a PCM link in UNI mode. If enabled,
a counter generates an interrupt request when it
overflows (i.e starts over from 0 after reaching the
maximum counter value). 6.1 Counter Block
paragraph for more details on the operation of the
counters. These 13 sources of overflow can be
identified through the IRQ Link FIFO Overflow and
IRQ UTOPIA FIFO Overflow status registers. Refer
to section 6.2.3 IRQ Link UNI Overflow and IRQ
UTOPIA Input UNI Overflow Status Registers for
more details.
Bits 7 (MSB) and 6 of the IRQ Link 0 Status register
have a special meaning.
Bit 7 reports an overflow condition in any of the
counters or UTOPIA RX FIFOs associated with one
of the four IMA Groups. Refer to 6.2.4 IRQ IMA
Group Overflow Status and Enable Registers for
more details. Bit 7 is a status bit and is cleared by
disabling the IRQ for this specific counter or
disabling (masking) the FIFO overflow condition by
writing to the RX UTOPIA IMA Group FIFO
Overflow Enable register.
Bit 6 is used to report the following two event types:
•
the ICP cell internal transfer is complete (reported
by any IMA Group TX ICP Cell Ready bit)
Reading the IRQ Link Status register does not clear
the source of interrupt. The bit 0 status is reset by
any one of the following procedures:
•
the end of an IMA frame on the reference link of an
IMA Group
•
•
disabling (masking) the IRQ for this specific counter
The second type of event assists in implementing the
software counter required to verify that Group Status
and Control field information is sent for at least 2
consecutive IMA frames.
clearing the overflow status bit in the IRQ Link UNI
Overflow and IRQ UTOPIA UNI Overflow Status
registers
•
disabling the interrupt in the RX UTOPIA Link
FIFO Overflow Enable or in the corresponding
Link (in UNI mode) Counter registers.
The
eight
interrupt
sources
are
enabled
independently by writing to the TX ICP Cell Handler
Enable register.
Bits 1, 2, 3, 4 and 5 of the IRQ Link Status register
are latches that report the source of an interrupt.
Writing a ’0’ these bits will reset the status bit (will
reset the latch). Writing ’0’ to bit 0 has no effect on
the status bit.
There is also an associated Control/Status register
(TX ICP Cell Handler register) that reports the
interrupt source and the state of the transfer of an
ICP Cell or the occurrence of the end of an IMA
frame. The Frame status bits are cleared by writing 0
to the bit. The Ready bit is set to 1 when the transfer
is complete. Bit 6 is a latched bit in the IRQ Link 0
Status register and is cleared by overwriting it with
0.
Writing a ’1’ has no effect on the bits 0 to 5 of the
IRQ Link Status register.
Each one of these six interrupt sources can be
enabled by writing a ’1’ in the IRQ Link Enable
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