Advance Information
MT89L86
Interface Mode Selection Register - Read/Write
7
6
5
4
3
2
1
0
DMO
IDR1
IDR0
ODR1 ODR0 SCB1 SCB0 CLKM
Bit
Name
Description
7
DMO
Device Main Operation. This bit is used by the CPU to define one of the two main
operations of the 3.3V MT89L86. If this bit is LOW, the MT89L86 is configured for
identical I/O data rates. For this operation, the user should also specify the switching
configuration through the SCB bits.
If this bit is HIGH, the MT89L86 is configured in Different I/O data rate. This allows
combinations of input and output data rates as shown in Table 2. The SCB bits have no
effect in this application and the device is in Non-Blocking switch configuration with a 256
x 256 channel capacity.
6-5
IDR1-0
Input Data Rate Selection. These two bits select three different data rates for the inputs
of the MT89L86. In the case of identical I/O rates (DMO bit = 0), these bits also
determine the serial output data rate.
IDR1
IDR0
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
reserved
0
0
1
1
0
1
0
1
4-3
ODR1-0 Output Data Rate Selection. These bits are only used when Different I/O rates are
selected (DMO bit=1). These two bits select three different data rates for the serial
outputs of the MT89L86. These bits are ignored if DMO bit = 0.
ODR1
ODR0
Output Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
reserved
0
0
1
1
0
1
0
1
2-1
0
SCB1-0
CLKM
Switching Configuration Bits 1-0. These bits should only be used when DMO is set
LOW. The use of these bits to select the switching configuration of the MT89L86 is
described in Table 8.
Clock Mode. This bit is only used when the MT89L86 is set to operate in identical I/O
data rates. When set High, this bit selects the interface clock to be equal to the bit rate. If
Low, this bit selects the interface clock to be twice the bit rate.
For Different I/O data rate applications, this bit is ignored.
Figure 4 - IMS Register Description
15
MITEL [ MITEL NETWORKS CORPORATION ]
