MT89L86
Advance Information
(CML) are output on the ST-BUS output streams
once every frame unless the ODE input pin is LOW.
If ME bit is HIGH, then the MT89L86 behaves as if
bits 2 (Message Channel) and 0 (Output Enable) of
every Connect Memory HIGH (CMH) locations were
set to HIGH, regardless of the actual value. If ME bit
is LOW, then bit 2 and 0 of each Connect Memory
HIGH location function normally. For example, if bit 2
of the CMH is HIGH, the associated ST-BUS output
channel is in Message mode. If bit 2 of the CMH is
LOW, then the contents of the SAB and CAB bits of
the CMH and CML define the source information
(stream and channel) of the time-slot that is to be
switched to an output.
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the matrices, and put all other
channels into the high impedance state. Care
should be taken that no two ST-BUS outputs drive
the bus simultaneously.
When this process is
complete, the microprocessor controlling the
matrices can bring the ODE signal high to relinquish
the high impedance state control to the OE bit of the
CMH (CMH 0s).
b
A RESET pin is available for the 48-pin SSOP
package. When this pin is set low for a minimum of
100n sec, the ST-BUS outputs are put to the high
impedance state and all register contents are set to
zero.
If the ODE input pin is LOW, then all serial outputs
are set to high impedance. If ODE is HIGH, then bit 0
(Output Enable) of the CMH location enables (if
HIGH) or disables (if LOW) the output drivers for the
corresponding individual ST-BUS output stream and
channel.
The contents of bit 1 (CSTo bit) of each Connection
Memory High location is output to the CSTo pin
once every frame. The CSTo pin is a 2048 Mbit/s
output which carries 256 bits. If CSTo bit is set HIGH,
the corresponding bit on CSTo output is transmitted
HIGH. If CSTo bit is LOW, the corresponding bit on
the CSTo output is transmitted LOW. The contents of
the 256 CSTo bits of the CMH are transmitted
sequentially to the CSTo output pin and are
synchronous to the 2.048 Mb/s ST-BUS streams. To
allow for delay in any external control circuitry the
contents of the CSTo bit is output one channel before
the corresponding channel on the ST-BUS streams.
For example, the contents of CSTo bit in position 0
(ST0, CH0) of the CMH, is transmitted
synchronously with ST-BUS channel 31, bit 7. The
contents of CSTo bit in position 32 (ST1, CH0) of the
CMH is transmitted during ST-BUS channel 31 bit 6.
For more detailed description of the CSTo operation,
see section 6 of Application Note MSAN-123.
The V/C bit (Variable/Constant Delay) of each
Connect Memory High location allows the per-
channel selection between Variable and Constant
throughput delay modes.
Initialization of the MT89L86
On initialization or power up, the contents of the
Connection Memory High can be in any state. This
is a potentially hazardous condition when multiple
MT89L86 ST-BUS outputs are tied together to form
matrices, as these outputs may conflict. The ODE
pin should be held low on power up to keep all
outputs in the high impedance condition.
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MITEL [ MITEL NETWORKS CORPORATION ]
