Advance Information
Control Register - Read/Write
MT89L86
7
SM
6
ME
5
STA3
4
MS1
3
MS0
2
STA2
1
STA1
0
STA0
Bit
7
Name
SM
Description
Split Memory.
When 1, all subsequent reads are from the Data Memory and writes are to
the Connection Memory Low, except when the Control Register is accessed again. When
0, the Memory Select bits specify the memory for subsequent operations. In either case,
the Stream Address Bits select the subsection of the memory which is made available.
Message Enable.
When 1, the contents of the Connection Memory Low are output on the
Serial Output streams except when in High Impedance as set by the ODE input. When 0,
the Connection Memory bits for each channel determine the output of the serial streams.
Stream Address Bit 3.
When the 16 x 8 switching configuration is selected, this pin is
used with STA2-0 to select one of the 16 input data streams whenever the Data Memory is
to be read. The programming of this bit has no effect in other switching configurations.
Memory Select Bits.
The memory select bits operate as follows:
0-0 - Not to be used
0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory Low
1-1 - Connection Memory High
The number expressed in binary notation on these bits refers to the input or output ST-BUS
stream which corresponds to the subsection of memory made accessible for subsequent
operations.
The use of these bits depends on the switching configuration as well as the device’s main
operation defined by the DMO bit of the Interface Mode Selection register. Tables 6 and 7
show the utilization of these bits according to the device’s main operation.
Figure 3 - Control Register Description
6
ME
5
STA3
4-3
MS1-0
2-0
STA2-0
13
MITEL [ MITEL NETWORKS CORPORATION ]
