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MT8979 参数 Datasheet PDF下载

MT8979图片预览
型号: MT8979
PDF下载: 下载PDF文件 查看货源
内容描述: ISO- CMOS ST- BUS⑩家庭CEPT PCM 30 / CRC - 4成帧器和接口 [ISO-CMOS ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface]
分类和应用: PC
文件页数/大小: 26 页 / 343 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8979 ISO-CMOS  
BIT  
7
NAME  
IU1  
DESCRIPTION  
International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in  
bit position 1 of timeslot 0 of non-frame-alignment frames . It is reserved for the CRC  
framing or as international bits.  
6
5
NFAF  
ALM  
Receive Non-Frame Alignment Bit: This is the bit which is received from the CEPT  
2048 kbit/s link in bit position 2 of timeslot 0 of non-frame-alignment frames . This bit  
should be ‘1‘ in order to differentiate between frame-alignment frames and  
non-frame-alignment frames.  
Non-Frame Alignment Alarm: This is the bit which is received from the CEPT 2048  
kbit/s link in bit position 3 of timeslot 0 of non-frame-alignment frames . It is used to signal  
an alarm from the remote end of the CEPT link. This bit should have the value ‘0‘ under  
normal operation and should go to ‘1 ‘to signal an alarm.  
4-0  
NU1-5  
National Use: These are the bits which are received on the CEPT 2048 kbit/s link in bit  
positions 4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for  
national use, and on crossing international borders they should have the value ‘1‘.  
Table 13. Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17  
BIT  
7
NAME  
DESCRIPTION  
TFSYN  
Frame Sync: This bit goes to ‘1‘ to indicate a loss of frame alignment synchronization by  
the MT8979. It goes to ‘0‘ when frame synchronization is detected.  
6
5
MFSYN  
ERR  
Multiframe Sync: This bit goes to ‘1‘ to indicate a loss of multiframe synchronization by  
the MT8979. It goes to ‘0‘ when multiframe synchronization is detected.  
Frame Alignment Error: This bit changes state when 16 or more errors have been  
detected in the frame alignment signal. It will not change state more than once every 128  
ms.  
4
3
SLIP  
Control Slip: This bit changes state when a slip occurs between the received CEPT  
2048 kbit/s link and the 2048 kbit/s ST-BUS.  
RXAIS  
Receive Alarm Indication Signal: This bit goes to ‘1‘ to signal that an all-ones alarm  
signal has been detected on the received CEPT 2048 kbit/s . It goes to ’0’ when the  
all-ones alarm signal is removed.  
2
RXTS16AIS Receive Timeslot 16 Alarm Indication Signal: This bit goes to ‘1‘ to signal that an  
all-ones alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s  
link. It goes to ’0’ when the all-ones alarm signal is removed.  
1
0
XS  
External Status: This bit contains the data sampled once per frame at the XS pin.  
N/A  
(Unused).  
Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18  
BIT  
NAME  
DESCRIPTION  
7 - 3  
TxTSC  
TxBTC  
Transmit Timeslot Count: The value of these five bits indicate the timeslot count  
between the ST-BUS frame pulse and the rising edge of E8Ko.  
2 - 0  
Transmit Bit Count:The value of these three bits indicate the bit position within the  
timeslot count reported in TxTSC above.  
Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19  
4-176  
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