MT8979 ISO-CMOS
Receiver
bipolar line driver and receiver have been simplified
for convenience as well as the addition of a clock
extractor and phase-lock loop. The clock extractor is
required to adjust the phase of the E2 clock in order
to sample the received data in the middle of the
pulse on RxD. The phase-lock loop, on the other
hand, will correct the system clocks to absorb the
low rate wander present on the line.
The receive line interface circuit shown in Figure 15
will decode the HDB3 line signals into two split
phase unipolar steering signals. These signals
are used to drive the violation detectors RxA and
RxB as well as being NAND‘ed to produce the
received data (RxD).
Please note: The configuration shown in Figure 16
using the MT8940 may not meet some international
standards for jitter performance. In cases where
strict idle jitter specifications must be met, a custom
phase-lock loop may be required.
The NAND gate was removed from the devices to
make the delay for the data path equal to the delay
of the clock path. This will optimize the jitter
performance of the receiver.
The typical connection diagram for the CEPT digital
trunk interface is provided in Figure 16.
The
+5V
•
MT8979
RxA
RxD
•
•
•
•
•
74LS00
RxT
RxR
:1
:1
+5V
•
1:
•
RxB
Figure 15 - Typical Bipolar Line Receiver
VDD
VDD
MT8979
MT8980
TxMF
STo0
STi0
DSTi
TxA
Line
Driver
DSTo
STo1
STo2
CSTo0
CSTi1
CSTo
TxB
STi1
F0i
C4i
F0i
C2i
•
RxA
RxD
Line
Receiver
E8Ko
•
RxB
E2i
MT8940
F0b
C4b
µP
Clock
Extractor
16.388
Crystal
Figure 16 - Typical Connection Diagram
4-178
MITEL [ MITEL NETWORKS CORPORATION ]
