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MT8976AC 参数 Datasheet PDF下载

MT8976AC图片预览
型号: MT8976AC
PDF下载: 下载PDF文件 查看货源
内容描述: ISO- CMOS ST- BUS⑩系列T1 / ESF成帧电路 [ISO-CMOS ST-BUS⑩ FAMILY T1/ESF Framer Circuit]
分类和应用:
文件页数/大小: 26 页 / 340 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8976 ISO-CMOS  
False Candidate  
Hunt Mode  
False  
Candidate  
Forced  
Reframe  
Candidate  
Out of  
Sync.  
False  
Candidate  
Verify  
Candidate  
Candidate  
CRC  
Check  
*
Candidate  
In sync  
Maintenance  
Valid Candidate  
Valid Candidate  
New Frame Position  
Resync  
Receiver  
* Note: Only when in ESF mode and CRC  
option is enabled.  
Figure 8 - Off-Line Framer State Diagram  
pointer and the ST-BUS read pointer will begin to  
decrease over time. When this delay approaches the  
minimum two channel threshold, the buffer will  
perform a controlled slip, which will reset the internal  
ST-BUS read pointers so that there is exactly 34  
channels delay between the two pointers. This will  
result in some ST-BUS channels containing  
information output in the previous frame. Repetition  
of up to one DS1 frame of information is possible.  
pointer, resulting in loss of up to one frame of  
received DS1 data.  
Note that when the device performs a controlled slip,  
the ST-BUS address pointers are repositioned so  
that there is either a 10 channel or a 34 channel  
delay between the input DS1 frame and the output  
ST-BUS frame. Since the buffer performs  
a
controlled slip only if the delay exceeds 42 channels  
or is less than 2 channels, there is an 8 channel  
hysteresis built into the slip mechanism. The device  
can, therefore, absorb 8 channels or 32.5µs of jitter  
in the received signal.  
Conversely, if the data on the DS1 side is being  
written into the buffer at a rate faster than that at  
which it is being read out on the ST-BUS side, the  
delay between the DS1 frame and the ST-BUS frame  
will increase over time. A controlled slip will be  
performed when the throughput delay exceeds 42  
ST-BUS channels. This slip will reset the internal ST-  
BUS counters so that there is a 10 channel delay  
between the DS1 write pointer and the ST-BUS read  
There is no loss of frame sync, multiframe sync or  
any errors in the signalling bits when the device  
performs a slip. The information on the FDL pins in  
ESF or SLC-96 mode will, however, undergo slips at  
the same time.  
4-42  
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