MT8952B ISO-CMOS
AC Electrical Characteristics† - Serial Port in Internal Timing Mode - (Figure 25)
Voltages are with respect to ground (V ) unless otherwise stated .
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Frame Pulse (F0i) width
t
50
30
20
ns
ns
ns
F0iW
Frame Pulse (F0i) setup time
Frame Pulse (F0i) hold time
t
See note 3.
F0iS
t
See note 3.
F0iH
t
SToZL
SToZH
CDSTo delay from clock input
125
ns
Test load circuit 1 (Fig. 26)
t
5
6
7
8
CDSTi setup time
CDSTi hold time
C2i clock period
C4i clock period
t
20
65
ns
ns
ns
ns
STiS
t
STiH
t
t
400
C2i
C4i
200
† Timing is over recommended temperature & power supply voltages (V =5V±5%, V =0V, T =–40 to 85°C).
DD
SS
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
F0iW
F0i
t
t
C4i
F0iH
CKi
(C4i)
t
C2i
t
F0iS
CKi
(C2i)
t
t
SToZL
SToZH
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
CDSTo
CDSTi
HIGH IMPEDANCE
t
STiH
t
STiS
Ch. 31
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
Figure 25 - Serial Port Input and Output in ST-BUS Format (Internal Timing Mode)
Note:
1. Channels 0 to 4 can only be active on CDSTi and CDSTo in the Internal Timing Mode.
2. Clock input CKi can be either of the ST-BUS clocks C2i (2.048MHz) or C4i (4.096 MHz) in the Internal Timing Mode.
3. The Frame Pulse set up and hold time measurements are to be referenced from the falling edge of C4i or the rising edge of C2i depending on
the clock selected.
V
DD
V
DD
A
B
Test
R =1kΩ
R =1kΩ
L
From
L
point
From
Test
output
From
output
point
Test
point
under test
S
output
1
under test
under test
C =
200 pF for
measurements
on Data Bus
150 pF for
measurements
on CDSTo
50 pF for
L
C
V
L
SS
C
L
C
L
Note: S is in position A
when measuring t
and in position B when
1
PLZ
others
measuring t
note below.
. See
PHZ
Test load circuit- 1
Test load circuit- 2
Test load circuit - 3
Figure 26 - Test Load Circuits
Note: Active Low to High impedance times are measured from the disabling signal edge to the time when Vout has increased by 0.5 volts. Active High to
High impedance times are measured from the disabling signal edge to the time when Vout has decreased by 0.5 volts.
3-82
MITEL [ MITEL NETWORKS CORPORATION ]
