MT8952B ISO-CMOS
AC Electrical Characteristics† - Serial Port, RESET, WD Timer and IRQ Release Time
(Figures 19, 20, 21 and 22). Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
Interrupt request release time
WD output delay HIGH to LOW
WD output delay LOW to HIGH
TEOP/REOP output delay
TEOP/REOP output hold time
CDSTo delay from CKi
t
120
135
135
110
110
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test load circuit 2 (Fig.26)
Test load circuit 1 (Fig.26)
Test load circuit 1 (Fig.26)
Test load circuit 1 (Fig.26)
Test load circuit 1 (Fig.26)
Test load circuit 1 (Fig.26)
IRQR
WDHL
WDLH
t
t
t
t
EOPD
EOPH
t
STOD
CDSTi setup time
t
20
65
STiS
CDSTi hold time
t
STiH
RESET pulse width
t
100
RST
† Timing is over recommended temperature & power supply voltages (V =5V±5%, V =0V, T =–40 to 85°C).
DD
SS
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
RST
RST
Figure 21 - RESET Timing
Flag or Idle Sequence
End Flag or Abort Sequence
CKi
t
STOD
CDSTo
TEOP
t
EOPH
t
EOPD
t
t
STiH
STiS
CDSTi
REOP
t
t
EOPH
EOPD
Figure 22 - Serial Port Input and REOP, Output and TEOP
Note: The frequency of the clock input CKi is assumed to be at the output bit rate. However, it can be at twice the bit rate in the Internal
Timing Mode.
3-80
MITEL [ MITEL NETWORKS CORPORATION ]
