MT8952B ISO-CMOS
AC Electrical Characteristics† - Microprocessor Interface - (Figures 17 and 18)
Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
Delay between CS and E clock
Cycle time
t
0
205
145
60
20
10
20
60
35
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSE
t
CYC
E Clock pulse width HIGH
E Clock pulse width LOW
Read/Write setup time
Read/Write hold time
Address setup time
t
EWH
t
EWL
RWS
RWH
t
t
t
AS
Address hold time
t
AH
Data setup time (write)
t
DSW
DHW
10 Data hold time (write)
t
11 E clock to valid data delay
t
t
145
60
Test load circuit 1 (Fig. 26)
DZL
DZH
ns
C =200pF
L
12 Data hold time (read)
t
t
10
DLZ
DHZ
ns
Test load circuit 3 (Fig. 26)
† Timing is over recommended temperature & power supply voltages (V =5V±5%, V =0V, T =–40 to 85°C).
DD
SS
A
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
CS
E clock initiates and
terminates the write cycle
t
CSE
t
EWH
E
t
EWL
t
t
f
r
t
CYC
CS
E
CS initiates and
terminates the write cycle
t
CSE
t
t
RWH
RWS
R/W
t
t
AH
AS
A0-A3
t
t
DHW
DSW
D0-D7
NOTE: The write cycle can be initiated either by the falling edge ofCS or the rising edge of E clock whichever occurs last. Similarly
the cycle can be terminated by CS (rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be
referenced from the active edge initiating or terminating the cycle
Figure 17 - Timing Information for MPU Write
3-78
MITEL [ MITEL NETWORKS CORPORATION ]
