ISO-CMOS MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 15)
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
F0b input pulse width (LOW)
C4b input clock period
t
40
.080
25
ns
µs
ns
ns
WFP
t
50
P4o
Frame pulse (F0b) setup time
t
FS
Frame pulse (F0b) hold time
t
5
FH
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
WFP
V
IH
F0b
C4b
V
IL
t
FH
V
IH
V
IL
t
FS
t
P4o
Figure 15 - External Inputs on C4b and F0b for the DPLL #2
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 16)
SS
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
Delay from Enable to Output
(HIGH to THREE STATE)
t
15
65
55
40
50
ns
ns
ns
ns
Test load circuit 3 (Fig.17)
PHZ
O
U
T
P
U
T
Delay from Enable to Output
(LOW to THREE STATE)
t
10
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
Test load circuit 3 (Fig.17)
PLZ
Delay from Enable to Output
(THREE STATE to HIGH)
t
PZH
Delay from Enable to Output
(THREE STATE to LOW)
t
PZL
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
6 ns
t
6 ns
f
r
3.0 V
2.7 V
1.3 V
0.3 V
Enable
Input
t
PZL
t
PLZ
Output
LOW to
OFF
1.3 V
10%
90%
t
PHZ
t
PZH
Output
HIGH
to OFF
1.3 V
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
Figure 16 - Three State Outputs and Enable Timings
3-41
MITEL [ MITEL NETWORKS CORPORATION ]
