ISO-CMOS
MT8940
AC Electrical Characteristics
†-Voltages are with respect to ground (V
SS
) unless otherwise stated.
(Ref. Figures 11&12)
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D
P
L
L
#2
C4b output delay (HIGH to
LOW) from C8Kb input/output
C4b output clock period
C4b output clock width (HIGH)
C4b output clock width (LOW)
C4b output clock rise time
C4b clock output fall time
Frame pulse output delay
(HIGH to LOW) from C4b
Frame pulse output delay
(LOW to HIGH) from C4b
Frame pulse (F0b) width
C4o delay - LOW to HIGH
C4o delay - HIGH to LOW
C4b to C2o delay (LOW to
HIGH)
C4b to C2o delay (HIGH to
LOW)
C2o clock period
C2o clock width (HIGH)
C2o clock width (LOW)
C2o clock rise time
C2o clock fall time
C2o delay - LOW to HIGH
C2o delay - HIGH to LOW
Sym
t
84H
t
P4o
t
W4oH
t
W4oL
t
rC4
t
fC4
t
FPL
t
FPH
t
WFP
t
4oLH
t
4oHL
t
42LH
t
42HL
t
P2o
t
W2oH
t
W2oL
t
rC2
t
fC2
t
2oLH
t
2oHL
-5
486
244
233
-10
200
Min
-25
240
123
110
Typ
‡
Max
75
282
165
123
10
10
50
40
245
45
45
+10
20
523
291
244
10
10
20
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 10).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test Conditions
Test load circuit 2 (Fig. 17)
on C8Kb.
Test load circuit 1 (Fig. 17).
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
C8Kb
as
Output
V
OH
V
OL
C8Kb
as
Input
V
IH
V
IL
t
84H
V
OH
t
W4oH
C4b
V
OL
t
P4o
t
FPL
V
OH
t
FPH
t
W4oL
F0b
V
OL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
3-39
MITEL [ MITEL NETWORKS CORPORATION ]
