ISO-CMOS MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 9)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
2
3
4
5
6
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
t
-40
75
15
ns
ns
ns
ns
ns
ns
F15H
CVb output (1.544 MHz) rise
time
t
10
12
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
r1.5
CVb output (1.544 MHz) fall
time
t
15
f1.5
P15
D
P
L
L
CVb output (1.544 MHz) clock
period
t
648
690
386
327
CVb output (1.544 MHz) clock
width (HIGH)
t
320
W15H
#1
CVb output (1.544 MHz) clock
width (LOW)
t
314
W15L
7
8
CV delay (HIGH to LOW)
t
5
30
10
ns
ns
15HL
15LH
CV delay (LOW to HIGH)
t
-12
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
V
V
IH
F0i
IL
t
F15H
t
P15
t
f1.5
t
W15H
V
V
OH
CVb
CV
OL
t
W15L
t
15HL
t
r1.5
t
15LH
V
V
OH
OL
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated. (Ref. Figure 10)
SS
‡
Characteristics
Sym
Min Typ
Max Units
Test Conditions
1
2
3
4
5
C8Kb output (8kHz) delay
(HIGH to HIGH)
t
130
130
ns
ns
Test load circuit 2 (Fig. 17).
C8HH
C8Kb output (8 kHz) delay
(LOW to LOW)
t
50
Test load circuit 2 (Fig. 17).
D
P
L
L
C8LL
C8Kb output duty cycle
66
50
%
%
In Divide -1 Mode
In Divide - 2 Mode
Inverted clock output delay
(HIGH to LOW)
#1
t
40
35
75
60
ns
ns
ICHL
ICLH
Inverted clock output delay
(LOW to HIGH)
t
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-37
MITEL [ MITEL NETWORKS CORPORATION ]
